Patent US5654926A successfully refreshed from Google Patents.
US5654926A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Renesas Design Corp
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Filing: 1996-02-22
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Granted: 1997-08-05
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Expires: 2016-02-22
Abstract
Abstract A semiconductor memory device pre-charges the electric potential of a selected bit line up to a predetermined electric potential, and judges the electric potential of the selected bit line on the basis of the predetermined electric potential as a threshold value after the pre-charge. Thereby, a semiconductor memory device capable of being read out at high speed can be realized.
Inventors
- 👤 Teruaki Kanzaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:17
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
278 words
A semiconductor memory device comprising: word lines; first bit lines; a plurality of first memory cells, each first memory cell being provided at a respective intersection of one of the word lines and one of the first bit lines and having a size; a bit line selecting circuit for selecting one of the first bit lines; pre-charging means for pre-charging one of the first bit lines selected by the bit line selecting circuit to a predetermined electrical potential, the pre-charging means including a first switching circuit for fixing the first bit lines at ground potential for a first period and for disconnecting the first bit lines from the ground potential during periods other than the first period, a second bit line separate from the first bit lines, a second switching circuit for connecting the second bit line to a power supply voltage during the first period, second memory cells provided at respective intersections of the word lines and the second bit line and having substantially the same size as the first memory cells, and a connecting circuit for connecting the first bit line selected by the bit line selecting circuit with the second bit line during a second period; a transistor for connecting the first bit line selected by the selecting circuit to a power supply after disconnecting the pre-charging means from the first bit line selected by the selecting circuit; and an output buffer circuit for indicating an electrical potential of the first bit line selected by the selecting circuit in response to the predetermined electrical potential as a threshold value after the first bit line selected by the selecting circuit is connected to the power supply.
Claim 2
Dependent Claim
278 words
A semiconductor memory device comprising: word lines; first bit lines; a plurality of first memory cells, each first memory cell being provided at a respective intersection of one of the word lines and one of the first bit lines and having a size; a bit line selecting circuit for selecting one of the first bit lines; pre-charging means for pre-charging one of the first bit lines selected by the bit line selecting circuit to a predetermined electrical potential, the pre-charging means including a first switching circuit for fixing the first bit lines at ground potential for a first period and for disconnecting the first bit lines from the ground potential during periods other than the first period, a second bit line separate from the first bit lines, a second switching circuit for connecting the second bit line to a power supply voltage during the first period, second memory cells provided at respective intersections of the word lines and the second bit line and having substantially the same size as the first memory cells, and a connecting circuit for connecting the first bit line selected by the bit line selecting circuit with the second bit line during a second period; a transistor for connecting the first bit line selected by the selecting circuit to a power supply after disconnecting the pre-charging means from the first bit line selected by the selecting circuit; and an output buffer circuit for indicating an electrical potential of the first bit line selected by the selecting circuit in response to the predetermined electrical potential as a threshold value after the first bit line selected by the selecting circuit is connected to the power supply.
Claim 3
Dependent Claim
54 words
The semiconductor memory device according to claim 1, wherein the transistor is configured to lower the electrical potential of the first bit line selected by the selecting circuit below the predetermined electrical potential when reading out binary information after the first bit line selected by the selecting circuit is connected to the power supply.
Claim 4
Dependent Claim
79 words
The semiconductor memory device according to claim 1, wherein each of the plurality of first and second memory cells comprises an N-channel MOS transistor having a grounded source, a drain connected to one of the first bit lines and to the second bit line, and a gate connected to one of the word lines, and wherein each of the memory cells has a threshold value set low when storing a logic 0 and high when storing a logic 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |