Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
238 words
A memory array of addressable MIS transistors arranged in row and columns, comprising: a semiconductor substrate of first conductivity type; a plurality of substantially parallel bit lines of a second conductivity type in said substrate; a plurality of channel regions in said substrate, each bounded in a direction of current flow by a pair of said bit lines; a first insulation layer over channel regions between at least first alternate sets of said bit lines; a conductive field shield layer overlying said first insulation layer and patterned to provide a plurality of electrical regions overlying at least portions of the channel regions between the first alternate sets of said bit lines, said field shield layer being configured to provide a plurality of substantially parallel stripes overlying the channel regions between the first alternate sets of said bit lines to define a plurality of channel regions for said MIS transistors between second alternate sets of said bit lines, said conductive field shield layer being biasable to establish nonconducting isolation transistors in said first alternate sets of said bit lines; a second insulation layer over at least said conductive field shield layer; a memory dielectric layer over at least the channel regions between the second alternate sets of said bit lines; a conductive gate layer, patterned to provide a plurality of stripes across the second insulation layer and the channel regions of said second alternate sets of said bit lines.
Claim 2
Dependent Claim
238 words
A memory array of addressable MIS transistors arranged in row and columns, comprising: a semiconductor substrate of first conductivity type; a plurality of substantially parallel bit lines of a second conductivity type in said substrate; a plurality of channel regions in said substrate, each bounded in a direction of current flow by a pair of said bit lines; a first insulation layer over channel regions between at least first alternate sets of said bit lines; a conductive field shield layer overlying said first insulation layer and patterned to provide a plurality of electrical regions overlying at least portions of the channel regions between the first alternate sets of said bit lines, said field shield layer being configured to provide a plurality of substantially parallel stripes overlying the channel regions between the first alternate sets of said bit lines to define a plurality of channel regions for said MIS transistors between second alternate sets of said bit lines, said conductive field shield layer being biasable to establish nonconducting isolation transistors in said first alternate sets of said bit lines; a second insulation layer over at least said conductive field shield layer; a memory dielectric layer over at least the channel regions between the second alternate sets of said bit lines; a conductive gate layer, patterned to provide a plurality of stripes across the second insulation layer and the channel regions of said second alternate sets of said bit lines.
Claim 3
Dependent Claim
24 words
The memory array of claim 1 further comprising means for biasing the field shield layer to a predetermined potential with respect to the substrate.
Claim 4
Dependent Claim
16 words
The memory array of claim 2 wherein said predetermined potential is the potential of the substrate.
Claim 5
Dependent Claim
32 words
The memory array of claim 1 wherein said substantially parallel field shield stripes additionally overlie at least a portion of the bit lines of said first alternate sets of said bit lines.
Claim 6
Dependent Claim
27 words
The memory array of claim 1 wherein said field shield layer is substantially self aligned with the channel regions of said second alternate sets of bit lines.
Claim 7
Dependent Claim
25 words
The memory array of claim 1 wherein said plurality of stripes of said conductive gate layer are substantially orthogonal to said parallel field shield stripes.
Claim 8
Dependent Claim
19 words
The memory array of claim 1 wherein said plurality of bit lines are lines of impurities in said substrate.
Claim 9
Dependent Claim
20 words
The memory array of claim 1 wherein said plurality of bit lines are double lines of impurities in said substrate.
Claim 10
Dependent Claim
16 words
The memory array of claim 1 wherein said conductive field shield layer is first level polysilicon.
Claim 11
Dependent Claim
15 words
The memory array of claim 1 wherein said conductive gate layer is second level polysilicon.
Claim 12
Dependent Claim
19 words
The memory array of claim 1 wherein said plurality of bit lines are substantially equidistantly spaced from one another.
Claim 13
Dependent Claim
15 words
The memory array of claim 1 wherein said memory dielectric is of a non-volatile material.
Claim 14
Dependent Claim
40 words
The memory array of claim 1 wherein said memory dielectric is selected from the group comprising oxides, oxynitrides, ferroelectric materials, silicon rich oxide, silicon nitride, silicon oxynitride, silicon rich silicon dioxide, tantalum pentoxide, carbides, ceramics, aluminum oxide, and silicon carbide.
Claim 15
Dependent Claim
14 words
The memory array of claim 1 wherein said memory dielectric comprises a multilayer dielectric.
Claim 16
Dependent Claim
48 words
The memory array of claim 14 wherein said multilayer memory dielectric includes at least one layer of non-volatile material selected from the group comprising oxides, oxynitrides, ferroelectric materials, silicon rich oxide, silicon nitride, silicon oxynitride, silicon rich silicon dioxide, tantalum pentoxide, carbides, ceramics, aluminum oxide, and silicon carbide.