Method and apparatus for reading ahead display data into a display FIFO of a graphics controller

Claim 2

In a computer system having a frame buffer and a system memory comprised in a single memory unit coupled to a bus, a method of displaying display data stored in the frame buffer comprising the steps of: monitoring the bus to determine whether the bus is idle; examining a display FIFO buffer to determine whether display data in the display FIFO buffer is below a low level water mark; examining a display FIFO buffer to determine whether display data in the display FIFO buffer has attained a high level water mark; transferring display data stored in the frame buffer into the display FIFO buffer over the bus if the bus is idle, transferring display data stored in the frame buffer to the display FIFO with a lower priority if the high level water mark is attained and the bus is idle, and transferring display data in the frame buffer into the display FIFO buffer with a higher priority if display data in the display FIFO buffer is below the low level water mark; and displaying display data stored in the display FIFO buffer.

Claim 3

The method of claim 1, wherein said step of monitoring said bus comprises the step of monitoring at least one of a set of RAS signals of the memory unit.

Claim 4

A graphics controller for displaying a display data stored in a frame buffer, the frame buffer and a system memory being comprised in a memory unit coupled to a bus, said graphics controller comprising: a display FIFO for storing the display data; a video controller for retrieving the display data from said display FIFO and sending the retrieved display data for display on a display unit; a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said memory unit; water mark determination means for determining whether a number of data items stored in said display FIFO is within a predetermined range; and a sequencer for retrieving the display data from said frame buffer if said bus is idle and for retrieving the display data from said frame buffer and storing the display data in said display FIFO if said number of data items stored in said display FIFO is within said predetermined range.

Claim 5

A graphics controller for displaying a display data stored in a frame buffer, the frame buffer and a system memory being comprised in a memory unit coupled to a bus, said graphics controller comprising: a display FIFO for storing the display data; a video controller for retrieving the display data from said display FIFO and sending the retrieved display data for display on a display unit; a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said memory unit; water mark determination means for determining whether a number of data items stored in said display FIFO is within a predetermined range; and a sequencer for retrieving the display data from said frame buffer if said bus is idle and for retrieving the display data from said frame buffer and storing the display data in said display FIFO if said number of data items stored in said display FIFO is within said predetermined range.

Claim 6

The graphics controller of claim 3, further comprising an MREQ generator for generating a low priority MREQ signal to a host controller controlling access to said bus.

Claim 7

The graphics controller of claim 4 wherein said MREQ generator generates a high priority MREQ signal to said host controller if said number of data items stored in said display FIFO is below a low level water mark.

Claim 8

A graphics controller for displaying a display data stored in a frame buffer, the frame buffer and a system memory being comprised in a memory unit coupled to a bus, said graphics controller comprising: a display FIFO for storing the display data; a video controller for retrieving the display data from said display FIFO and sending the retrieved display data for display on a display unit; a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said memory unit; and a sequencer for retrieving the display data from said frame buffer if said bus is idle; a water mark determination means for determining whether a number of data items stored in said display FIFO is within a predetermined range; and an MREQ generator for generating a low priority MREQ signal to a host controller controlling access to said bus, wherein said sequencer initiates retrieval of the display data from said frame buffer and stores in said display FIFO if said number of data items stored in said display FIFO is within said predetermined range, said MREQ generator generates a high priority MREQ signal to said host controller if said number of data items stored in said display FIFO is below a low level water mark, and said host controller is designed to give a high priority to said high priority MREQ signal, and a low priority to said low priority MREQ signal.

Claim 9

A graphics controller for displaying a display data stored in a frame buffer, the frame buffer and a system memory being comprised in a memory unit coupled to a bus, said graphics controller comprising: a display FIFO for storing the display data; a video controller for retrieving the display data from said display FIFO and sending the retrieved display data for display on a display unit; a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said memory unit; and a sequencer for retrieving the display data from said frame buffer if said bus is idle; a water mark determination means for determining whether a number of data items stored in said display FIFO is within a predetermined range; and an MREQ generator for generating a low priority MREQ signal to a host controller controlling access to said bus, wherein said sequencer initiates retrieval of the display data from said frame buffer and stores in said display FIFO if said number of data items stored in said display FIFO is within said predetermined range, said MREQ generator generates a high priority MREQ signal to said host controller if said number of data items stored in said display FIFO is below a low level water mark, and said host controller is designed to give a high priority to said high priority MREQ signal, and a low priority to said low priority MREQ signal.

Claim 10

The graphics controller of claim 6 wherein said water mark determination means comprises: a high level water mark register for storing the predetermined range; a low level water mark register for storing the low level water mark; a flip-flop for indicating whether to generate the low level low priority MREQ signal; a display FIFO level counter for storing a count indicative of the number of data items; a first comparator coupled to said display FIFO level counter and to said high level water mark register for determining whether the count of said display FIFO level counter is within the predetermined range; and a second comparator coupled to said display FIFO level counter and to said low level water mark register for determining whether the count of said display FIFO level counter is below said low level water mark.

Claim 11

The graphics controller of claim 7, wherein said first comparator comprises a first plurality of XNOR gates, each of said first plurality of XNOR gates being coupled to receive a bit of said high level water mark register and a bit of said display FIFO level counter, the outputs of said XNOR gates being coupled to an AND gate, wherein output of said AND gate is coupled to an input of said flip-flop.

Claim 12

The graphics controller of claim 8, wherein said second comparator comprises a second plurality of XNOR gates, each of said second plurality of XNOR gates being coupled to receive a bit of said low level water mark register and one of a least significant bits of said display FIFO level counter.

Claim 13

The graphics controller of claim 7, wherein said low level water mark register and said high level water mark register are programmable.

Claim 14

The graphics controller of claim 7, wherein said low level water mark register and said high level water mark register comprise a lesser number of bits than said display FIFO level counter.

Claim 15

A computer system comprising: a frame buffer coupled to a bus; a host controller for receiving MREQ signals and granting access to said bus; a CPU for sending display data; a graphics controller coupled to receive the display data and to store the display data into said frame buffer, retrieving display data into a display FIFO prior to display on a display unit, sending to said host controller a low priority MREQ signal if said bus is idle and a high priority MREQ signal if data stored in said display FIFO falls below a low level water mark, wherein said host controller grants access to said graphics controller with a lower priority in response to said low priority MREQ signal and with a high priority in response to said high priority MREQ signal, and said graphics controller transfers the display data to said display FIFO upon being granted access to said bus.

Claim 16

A computer system comprising: a frame buffer coupled to a bus; a host controller for receiving MREQ signals and granting access to said bus; a CPU for sending display data; a graphics controller coupled to receive the display data and to store the display data into said frame buffer, retrieving display data into a display FIFO prior to display on a display unit, sending to said host controller a low priority MREQ signal if said bus is idle and a high priority MREQ signal if data stored in said display FIFO falls below a low level water mark, wherein said host controller grants access to said graphics controller with a lower priority in response to said low priority MREQ signal and with a high priority in response to said high priority MREQ signal, and said graphics controller transfers the display data to said display FIFO upon being granted access to said bus.

Claim 17

The computer system of claim 12, wherein said graphics controller comprises a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said frame buffer.

Claim 18

The computer system of claim 13, wherein said graphics controller sends a low priority MREQ signal if display data stored in said display FIFO falls below a high water mark level.

Claim 19

The computer system of claim 14, wherein said graphics controller further comprises a water mark determination means to determine whether display data in said display FIFO is below the low level water mark and the high level water mark.

Claim 20

A computer system computer system comprising: a frame buffer coupled to a bus; a host controller for receiving MREQ signals and granting access to said bus; a CPU for sending display data; a graphics controller coupled to receive the display data and to store the display data into said frame buffer, retrieving display data into a display FIFO prior to display on a display unit, sending to said host controller a low priority MREQ signal if said bus is idle and a high priority MREQ signal if data stored in said display FIFO falls below a low level water mark; said graphics controller comprising a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said frame buffer, a water mark determination means to determine whether display data in said display FIFO is below the low level water mark and the high level water mark, wherein said water mark determination means comprises: a high level water mark register for storing the high level water mark; a low level water mark register for storing the low level water mark; a flip-flop for indicating whether to generate said low priority MREQ signal; a display FIFO level counter for storing a count indicative of a number of data items stored in the display FIFO; a first comparator coupled to said display FIFO level counter and to said high level water mark register for determining whether the count is within said predetermined range; and a second comparator coupled to said display FIFO level counter and to said low level water mark register for determining whether the count is below said low level priority counter, wherein said host controller grants access to said graphics controller with a lower priority in response to said low priority MREQ signal and with a high priority in response to said high priority MREQ signal, said graphics controller transfers the display data to said display FIFO upon being granted access to said bus, and said graphics controller sends a low priority MREQ signal if display data stored in said display FIFO falls below a high water mark level.

Claim 21

A computer system computer system comprising: a frame buffer coupled to a bus; a host controller for receiving MREQ signals and granting access to said bus; a CPU for sending display data; a graphics controller coupled to receive the display data and to store the display data into said frame buffer, retrieving display data into a display FIFO prior to display on a display unit, sending to said host controller a low priority MREQ signal if said bus is idle and a high priority MREQ signal if data stored in said display FIFO falls below a low level water mark; said graphics controller comprising a RAS snooper for determining whether said bus is idle by examining a set of RAS signal lines of said frame buffer, a water mark determination means to determine whether display data in said display FIFO is below the low level water mark and the high level water mark, wherein said water mark determination means comprises: a high level water mark register for storing the high level water mark; a low level water mark register for storing the low level water mark; a flip-flop for indicating whether to generate said low priority MREQ signal; a display FIFO level counter for storing a count indicative of a number of data items stored in the display FIFO; a first comparator coupled to said display FIFO level counter and to said high level water mark register for determining whether the count is within said predetermined range; and a second comparator coupled to said display FIFO level counter and to said low level water mark register for determining whether the count is below said low level priority counter, wherein said host controller grants access to said graphics controller with a lower priority in response to said low priority MREQ signal and with a high priority in response to said high priority MREQ signal, said graphics controller transfers the display data to said display FIFO upon being granted access to said bus, and said graphics controller sends a low priority MREQ signal if display data stored in said display FIFO falls below a high water mark level.

Claim 22

The computer system of claim 16, wherein said first comparator comprises a first plurality of XNOR gates, each of said first plurality of XNOR gates being coupled to receive a bit of said high level water mark register and a bit of said display FIFO level counter, the outputs of said XNOR gates being coupled to an AND gate, wherein output of said AND gate is coupled to an input of said flip-flop.

Claim 23

The computer system of claim 17, wherein said second comparator comprises a second plurality of XNOR gates, each of said second plurality of XNOR gates being coupled to receive a bit of said low level water mark register and one of a least significant bits of said display FIFO level counter.

Claim 24

The computer system of claim 16, wherein said low level water mark register and said high level water mark register are programmable.

Claim 25

The computer system of claim 16, wherein said low level water mark register and said high level water mark register comprise a lesser number of bits than said display FIFO level counter.