Patent US5657241A successfully refreshed from Google Patents.
US5657241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Routing methods for use in a logic emulation system
Assignee: Cadence Design Systems Inc
•
Filing: 1995-06-06
•
Granted: 1997-08-12
•
Expires: 2015-06-06
Abstract
Abstract A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
Inventors
- 👤 Michael R. Butts
- 👤 Jon A. Batcheller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:15
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/347; G06F30/39
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
344 words
A method for routing a design into a hardware logic emulation system, the design comprising a user-provided netlist description, the user-provided netlist description comprising a first set of primitives, the hardware logic emulation system comprising a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, at least some other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected electrically reconfigurable devices containing functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices containing functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices containing functional logic elements, the method comprising the steps of: converting the user-provided netlist description into an emulation netlist, said emulation netlist being functionally equivalent the user-provided netlist but having primitives compatible with the functional logic elements of said electrically reconfigurable devices; partitioning said emulation netlist into a plurality of partitions, each of said plurality partitions comprising a subset of the primitives of said emulation netlist; issuing first statements for each primitive within each partition of said plurality of partitions of said emulation netlist, said first statements defining where said primitive is to be placed within said electrically reconfigurable devices containing reprogrammable functional logic elements; listing cut nets, each of said cut nets comprising a net which will have to pass from a first of said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements, through a first of said electrically reconfigurable devices containing reprogrammable electrical conductors, to a second of said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements; selecting said electrically reconfigurable devices containing reprogrammable electrical conductors which can best interconnect said cut nets; and issuing statements for each of said cut nets which define where each of said cut nets is placed in the selected electrically reconfigurable devices containing reprogrammable electrical conductors.
Claim 2
Independent Claim
344 words
A method for routing a design into a hardware logic emulation system, the design comprising a user-provided netlist description, the user-provided netlist description comprising a first set of primitives, the hardware logic emulation system comprising a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, at least some other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected electrically reconfigurable devices containing functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices containing functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices containing functional logic elements, the method comprising the steps of: converting the user-provided netlist description into an emulation netlist, said emulation netlist being functionally equivalent the user-provided netlist but having primitives compatible with the functional logic elements of said electrically reconfigurable devices; partitioning said emulation netlist into a plurality of partitions, each of said plurality partitions comprising a subset of the primitives of said emulation netlist; issuing first statements for each primitive within each partition of said plurality of partitions of said emulation netlist, said first statements defining where said primitive is to be placed within said electrically reconfigurable devices containing reprogrammable functional logic elements; listing cut nets, each of said cut nets comprising a net which will have to pass from a first of said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements, through a first of said electrically reconfigurable devices containing reprogrammable electrical conductors, to a second of said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements; selecting said electrically reconfigurable devices containing reprogrammable electrical conductors which can best interconnect said cut nets; and issuing statements for each of said cut nets which define where each of said cut nets is placed in the selected electrically reconfigurable devices containing reprogrammable electrical conductors.
References Cited (Backward Citations)
US3106698A
Cited
US3287703A
Cited
US3287702A
Cited
US3473160A
Cited
US4020469A
Cited
US4306286A
Cited
US4386403A
Cited
US4488354A
Cited
US4503386A
Cited
JPS58205870A
Cited
US4656580A
Cited
US4541071A
Cited
JPS59161839A
Cited
US4578761A
Cited
US4791602A
Cited
US4612618A
Cited
US4621339A
Cited
US4593363A
Cited
US4577276A
Cited
US4675832A
Cited
US4656592A
Cited
US4870302A
Cited
US4695999A
Cited
US4949275A
Cited
US4642487A
Cited
US5023775A
Cited
US4758985A
Cited
US4706216A
Cited
US4697241A
Cited
US4752887A
Cited
US4747102A
Cited
US4942536A
Cited
US4740919A
Cited
US4935734A
Cited
GB2180382A
Cited
US4882690A
Cited
US4803636A
Cited
US4722084A
Cited
US4700187A
Cited
US4918594A
Cited
US4835705A
Cited
US4744084A
Cited
US4823276A
Cited
US4862347A
Cited
US4777606A
Cited
US5126966A
Cited
US4736338A
Cited
US4945503A
Cited
US4768196A
Cited
US4918440A
Cited
US4811214A
Cited
US4786904A
Cited
US4682440A
Cited
US4849928A
Cited
US4942615A
Cited
US4924429A
Cited
US4827427A
Cited
US4965739A
Cited
US4908772A
Cited
US4877061A
Cited
US4815003A
Cited
US4849904A
Cited
US5093920A
Cited
US4872125A
Cited
US4951220A
Cited
US4901260A
Cited
US4876466A
Cited
JPH01154251A
Cited
US5046017A
Cited
US4922432A
Cited
US5197016A
Cited
US5053980A
Cited
US4931946A
Cited
US4914612A
Cited
US5003487A
Cited
US4901259A
Cited
US5041986A
Cited
US5109353A
Cited
US5140526A
Cited
US5051938A
Cited
US5233539A
Cited
US5231588A
Cited
US5081602A
Cited
US5231589A
Cited
US5146460A
Cited
US5128871A
Cited
US5084824A
Cited
US5258932A
Cited
US5193068A
Cited
US5272651A
Cited
US5189628A
Cited
US5467462A
Cited
US5224056A
Cited
US5452227A
Cited
US5425036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |