Apparatus for computing delay time of integrated circuit

Claim 1

An apparatus for computing delay times of integrated circuits, comprising: a data base storing data on various cells to be used in designing integrated circuits; input unit operable by a designer to redesign a circuit under design; and a processing unit coupled to said data base and said input means, said processing unit including: a data input interface, coupled to said input unit, controlling the transfer of input data from said input unit, a signal path building section, coupled to said data input interface, receiving circuit design data input by the designer on a redesigned circuit, and reconstructing a new signal propagation path coupling a cell affected by the redesign of circuit by referring to the data input by the designer, and a signal delay time computing section, coupled to said signal path building section, computing a signal delay time for the cells coupled along the new signal propagation path while reconstructing the new signal propagation path.

Claim 2

An apparatus for computing delay times of integrated circuits, comprising: a data base storing data on various cells to be used in designing integrated circuits; input unit operable by a designer to redesign a circuit under design; and a processing unit coupled to said data base and said input means, said processing unit including: a data input interface, coupled to said input unit, controlling the transfer of input data from said input unit, a signal path building section, coupled to said data input interface, receiving circuit design data input by the designer on a redesigned circuit, and reconstructing a new signal propagation path coupling a cell affected by the redesign of circuit by referring to the data input by the designer, and a signal delay time computing section, coupled to said signal path building section, computing a signal delay time for the cells coupled along the new signal propagation path while reconstructing the new signal propagation path.

Claim 8

A method of computing delay times of signals used in integrated circuits using a computer aided design system including a data base, input unit and processing unit, said method comprising the steps of: inputting data about the redesign of a circuit cell as an element of a circuit; constructing a, new signal propagation path for the redesigned circuit cell by referring to the data input to said input unit by a circuit designer; computing a delay time of the cell affected by the circuit redesign and included in the new signal propagation paths, every time the new path is constructed.

Claim 9

A method of computing delay times of signals used in integrated circuits using a computer aided design system including a data base, input unit and processing unit, said method comprising the steps of: inputting data about the redesign of a circuit cell as an element of a circuit; constructing a, new signal propagation path for the redesigned circuit cell by referring to the data input to said input unit by a circuit designer; computing a delay time of the cell affected by the circuit redesign and included in the new signal propagation paths, every time the new path is constructed.

Claim 10

A method of computing delay times of signals used in integrated circuits using a computer aided design system including a data base, input unit and processing unit having a delay time computing section, said method comprising the steps of: inputting data about the redesign of a circuit cell as an element of a circuit; constructing a new signal propagation path for the redesigned circuit cell by referring to the data input to said input unit by a circuit designer; and computing a delay time of the cell affected by the circuit redesign and included in the new signal propagation path, every time the new path is constructed, wherein the cell data, stored in said data base, includes a total delay time computation equation and parameters corresponding to the propagation delay of an input signal to a cell, and wherein at the time of computing the delay time of the cell involved in circuit redesign, said delay time computing section uses the propagation delay value determined at the output of a cell preceding the redesigned cell as the propagation delay value at the input of the redesigned cell, and computes the delay time of the redesigned cell based on said total delay time computation equation and parameters.

Claim 11

A method of computing delay times of signals used in integrated circuits using a computer aided design system including a data base, input unit and processing unit having a delay time computing section, said method comprising the steps of: inputting data about the redesign of a circuit cell as an element of a circuit; constructing a new signal propagation path for the redesigned circuit cell by referring to the data input to said input unit by a circuit designer; and computing a delay time of the cell affected by the circuit redesign and included in the new signal propagation path, every time the new path is constructed, wherein the cell data, stored in said data base, includes a total delay time computation equation and parameters corresponding to the propagation delay of an input signal to a cell, and wherein at the time of computing the delay time of the cell involved in circuit redesign, said delay time computing section uses the propagation delay value determined at the output of a cell preceding the redesigned cell as the propagation delay value at the input of the redesigned cell, and computes the delay time of the redesigned cell based on said total delay time computation equation and parameters.