US5664152A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple segmenting of main memory to streamline data paths in a computing system
Assignee: Hewlett Packard Development Co LP
•
Filing: 1995-06-06
•
Granted: 1997-09-02
•
Expires: 2015-06-06
Abstract
Abstract Within a computing system, the main memory is segmented in order to streamline data paths for data transactions between input/output devices. The computing system includes both a host bus and an input/output bus. One or more processors are connected to the host bus. A bus bridge connects the input/output bus to the host bus. The bus bridge is used for transferring information between the host bus and the input/output bus. The main memory for the computing system is segmented as follows. A first main memory segment is connected to the host bus. A second main memory segment is connected to the input/output bus. The first main memory segment and the second main memory segment are configured to appear to the processors as a single logical memory image. The segmented main memory is used to streamline data paths for the computing system. For example, a data transfer between a first input/output device and a second input/output device is controlled by the processor; however, during the first data transfer, the data itself is temporarily stored in the second main memory segment. This allows the data transfer to occur with only control information flowing through the bus bridge. The actual data is transported only on the input/output bus between the second main memory segment and the first input/output device, and between the second main memory segment and the second input/output device.
Inventors
- 👤 Ali Ezzet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:01
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/404
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
116 words
A computing system comprising: a host bus, the host bus transferring both addresses and data; a processor, coupled to the host bus; an input/output bus, the input/output bus transferring both address and data; a bus bridge coupled between the input/output bus and the host bus, the bus bridge being used for transferring information between the host bus and the input/output bus; and, a main memory for the computing system comprising, a first main memory segment coupled to the host bus, and a second main memory segment coupled to the input/output bus, wherein the first main memory segment and the second main memory segment are configured to appear to the processor as a single logical memory image.
Claim 2
Dependent Claim
116 words
A computing system comprising: a host bus, the host bus transferring both addresses and data; a processor, coupled to the host bus; an input/output bus, the input/output bus transferring both address and data; a bus bridge coupled between the input/output bus and the host bus, the bus bridge being used for transferring information between the host bus and the input/output bus; and, a main memory for the computing system comprising, a first main memory segment coupled to the host bus, and a second main memory segment coupled to the input/output bus, wherein the first main memory segment and the second main memory segment are configured to appear to the processor as a single logical memory image.
Claim 3
Dependent Claim
64 words
A computing system as in claim 1 additionally comprising: a first input/output device coupled to the input/output bus; and a second input/output device coupled to the input/output bus, wherein a first data transfer between the first input/output device and the second input/output device is controlled by the processor, and during the first data transfer, transferred data is stored in the second main memory segment.
Claim 4
Dependent Claim
92 words
A computer system as in claim 2 additionally comprising: a second input/output bus; and a second bus bridge coupled between the second input/output bus and the host bus, the second bus bridge being used for transferring information between the host bus and the second input/output bus; wherein the main memory additionally comprises a third main memory segment, coupled to the second input/output bus, the first main memory segment, the second main memory segment and the third main memory segment being configured to appear to the processor as a single logical memory image.
Claim 5
Dependent Claim
66 words
A computing system as in claim 3 additionally comprising: a third input/output device coupled to the second input/output bus; and a fourth input/output device coupled to the second input/output bus, wherein a second data transfer between the third input/output device and the fourth input/output device is controlled by the processor, and during the second data transfer, transferred data is stored in the third main memory segment.
Claim 6
Dependent Claim
43 words
A computing system as in claim 3 wherein a third data transfer from the third input/output device to the second input/output device is controlled by the processor, and during the third data transfer, transferred data is stored in the second main memory segment.
Claim 7
Dependent Claim
19 words
A computing system as in claim 1 wherein the input/output bus operates in accordance to a PCI bus standard.
Claim 8
Dependent Claim
60 words
A computer system as in claim 2 additionally comprising: a second input/output bus; and a second bus bridge coupled between the second input/output bus and the host bus, the second bus bridge being used for transferring information between the host bus and the second input/output bus; wherein the second main memory segment is additionally coupled to the second input/output bus.
Claim 9
Dependent Claim
66 words
A computing system as in claim 7 additionally comprising: a third input/output device coupled to the second input/output bus; and a fourth input/output device coupled to the second input/output bus, wherein a second data transfer between the third input/output device and the fourth input/output device is controlled by the processor, and during the second data transfer, transferred data is stored in the second main memory segment.
Claim 10
Dependent Claim
43 words
A computing system as in claim 8 wherein a third data transfer from the third input/output device to the second input/output device is controlled by the processor, and during the third data transfer, transferred data is stored in the second main memory segment.
Claim 11
Independent Claim
168 words
A method for performing a data transfer from a first input/output device connected to a first input/output bus to a second input/output device connected to the input/output bus, comprising the steps of: (a) configuring a first main memory segment connected to a host bus and a second main memory segment connected to the input/output bus to appear to an operating system for the computing system as a single logical memory image; (b) sending control information between the first input/output device and a processor connected to the host bus, the control information passing through a bus bridge connected between the input/output bus and the host bus; (c) transferring data from the first input/output device to the second main memory segment, the data not passing through the bus bridge connected between the input/output bus and the host bus; and, (d) transferring data from the second main memory segment to the second input/output device, the data not passing through the bus bridge connected between the input/output bus and the host bus.
Claim 12
Independent Claim
168 words
A method for performing a data transfer from a first input/output device connected to a first input/output bus to a second input/output device connected to the input/output bus, comprising the steps of: (a) configuring a first main memory segment connected to a host bus and a second main memory segment connected to the input/output bus to appear to an operating system for the computing system as a single logical memory image; (b) sending control information between the first input/output device and a processor connected to the host bus, the control information passing through a bus bridge connected between the input/output bus and the host bus; (c) transferring data from the first input/output device to the second main memory segment, the data not passing through the bus bridge connected between the input/output bus and the host bus; and, (d) transferring data from the second main memory segment to the second input/output device, the data not passing through the bus bridge connected between the input/output bus and the host bus.
Claim 13
Dependent Claim
25 words
A computing system as in claim 10 wherein in step (c) and step (d) the input/output bus operates in accordance to a PCI bus standard.
Claim 14
Independent Claim
181 words
A method for performing data transfers between input/output devices, comprising the steps of: (a) configuring a first main memory segment connected to a host bus and a second main memory segment connected to a first input/output bus to appear to an operating system for the computing system as a single logical memory image; and, (b) performing a first data transfer, including the following substeps, (b.1) sending first control information between a first input/output device connected to the first input/output bus and a processor connected to the host bus, the first control information passing through a first bus bridge connected between the first input/output bus and the host bus, (b.2) transferring data from the first input/output device to the second main memory segment, the data not passing through the first bus bridge connected between the first input/output bus and the host bus, and (b.3) transferring data from the second main memory segment to a second input/output device connected to the first input/output bus, the data not passing through the first bus bridge connected between the first input/output bus and the host bus.
Claim 15
Independent Claim
181 words
A method for performing data transfers between input/output devices, comprising the steps of: (a) configuring a first main memory segment connected to a host bus and a second main memory segment connected to a first input/output bus to appear to an operating system for the computing system as a single logical memory image; and, (b) performing a first data transfer, including the following substeps, (b.1) sending first control information between a first input/output device connected to the first input/output bus and a processor connected to the host bus, the first control information passing through a first bus bridge connected between the first input/output bus and the host bus, (b.2) transferring data from the first input/output device to the second main memory segment, the data not passing through the first bus bridge connected between the first input/output bus and the host bus, and (b.3) transferring data from the second main memory segment to a second input/output device connected to the first input/output bus, the data not passing through the first bus bridge connected between the first input/output bus and the host bus.
Claim 16
Dependent Claim
22 words
A method as in claim 12 wherein in step (b) the first input/output bus operates in accordance with a PCI bus standard.
Claim 17
Dependent Claim
52 words
A computing system as in claim 12 wherein step (a) includes configuring a third main memory segment, connected to a second input/output bus, together with the first main memory segment and the second main memory segment to appear to the operating system for the computing system as the single logical memory image.
Claim 18
Dependent Claim
138 words
A method as in claim 14 additionally including the following step: (c) performing a second data transfer, including the following substeps, (c.1) sending second control information between a third input/output device connected to the second input/output bus and a processor connected to the host bus, the second control information passing through a second bus bridge connected between the second input/output bus and the host bus, (c.2) transferring data from the third input/output device to the third main memory segment, the data not passing through the second bus bridge connected between the second input/output bus and the host bus, and (c.3) transferring data from the third main memory segment to a fourth input/output device connected to the second input/output bus, the data not passing through the second bus bridge connected between the second input/output bus and the host bus.
Claim 19
Dependent Claim
128 words
A computing system as in claim 14 additionally including the following step: (c) performing a second data transfer, including the following substeps, (c.1) sending second control information between a third input/output device connected to the second input/output bus and a processor connected to the host bus, the second control information passing through a second bus bridge connected between the second input/output bus and the host bus, (c.2) transferring data from the third input/output device to the second main memory segment, the data passing through the second bus bridge and through the first bus bridge, and (c.3) transferring data from the second main memory segment to the first input/output device, without the data passing through the first bus bridge connected between the second input/output bus and the host bus.
Claim 20
Dependent Claim
23 words
A computing system as in claim 12 wherein in step (a) the second main memory segment is connected to a second input/output bus.
Claim 21
Dependent Claim
138 words
A method as in claim 17 additionally including the following step: (c) performing a second data transfer, including the following substeps, (c.1) sending second control information between a third input/output device connected to the second input/output bus and a processor connected to the host bus, the second control information passing through a second bus bridge connected between the second input/output bus and the host bus, (c.2) transferring data from the third input/output device to the second main memory segment, the data not passing through the second bus bridge connected between the second input/output bus and the host bus, and (c.3) transferring data from the second main memory segment to a fourth input/output device connected to the second input/output bus, the data not passing through the second bus bridge connected between the second input/output bus and the host bus.
Claim 22
Dependent Claim
153 words
A computing system as in claim 17 additionally including the following step: (c) performing a second data transfer, including the following substeps, (c.1) sending second control information between a third input/output device connected to the second input/output bus and a processor connected to the host bus, the second control information passing through a second bus bridge connected between the second input/output bus and the host bus, (c.2) transferring data from the third input/output device to the second main memory segment, without the data passing through the second bus bridge connected between the second input/output bus and the host bus, and without the data passing through the first bus bridge connected between the first input/output bus and the host bus, and (c.3) transferring data from the second main memory segment to the first input/output device, without the data passing through the first bus bridge connected between the first input/output bus and the host bus.
References Cited (Backward Citations)
US4700292A
Cited
US4646237A
Cited
EP0207472A2
Cited
US4764896A
Cited
US4855902A
Cited
US5287485A
Cited
US5274795A
Cited
US5483642A
Cited
US5416907A
Cited
US5584004A
Cited
US5269005A
Cited
US5379384A
Cited
US5355452A
Cited
US5367701A
Cited
JPH07121474A
Cited
US5548730A
Cited
US5603051A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |