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Patent US5665995A successfully refreshed from Google Patents.
US5665995A
Expired / Lapsed
US
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Post passivation programmed mask ROM
Assignee: United Microelectronics Corp
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Filing: 1995-04-27
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Granted: 1997-09-09
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Expires: 2015-04-27
Abstract
Abstract A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 ANGSTROM . Glass insulation having a thickness of about 3000 ANGSTROM or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 ANGSTROM , precede activation of the impurity ions by annealing the device at less than or equal to about 520 DEG C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Shing-Ren Shev
- 👤 Kuan-Cheng Su
- 👤 Chen-Hui Chung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:08
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
179 words
An array of read only memory cells, comprising: a semiconductor substrate doped to a first conductivity type having a surface; a layer of insulating material on the surface of the semiconductor substrate; first, second and third gate electrodes spaced laterally over the layer of insulating material, each of the gate electrodes having an upper gate electrode surface; a first insulating glass layer over each of the upper gate electrode surfaces and over the layer of insulating material between the first and second and between the second and third gate electrodes; second doped insulating glass layers on the first insulating glass layer between the first and second gate electrodes and between the second and third gate electrodes, the second doped insulating glass layers extending below the upper gate electrode surfaces and localized so that the second doped glass layers do not extend over the first, second and third gate electrodes, the first insulating glass layer and the second doped insulating glass layers providing a planarized surface above the upper gate electrode surfaces; and a passivation layer over the planarized surface.
Claim 2
Dependent Claim
179 words
An array of read only memory cells, comprising: a semiconductor substrate doped to a first conductivity type having a surface; a layer of insulating material on the surface of the semiconductor substrate; first, second and third gate electrodes spaced laterally over the layer of insulating material, each of the gate electrodes having an upper gate electrode surface; a first insulating glass layer over each of the upper gate electrode surfaces and over the layer of insulating material between the first and second and between the second and third gate electrodes; second doped insulating glass layers on the first insulating glass layer between the first and second gate electrodes and between the second and third gate electrodes, the second doped insulating glass layers extending below the upper gate electrode surfaces and localized so that the second doped glass layers do not extend over the first, second and third gate electrodes, the first insulating glass layer and the second doped insulating glass layers providing a planarized surface above the upper gate electrode surfaces; and a passivation layer over the planarized surface.
Claim 3
Dependent Claim
22 words
The array of claim 1, wherein the gate electrodes are 3000 Å or less in height about the layer of insulating material.
Claim 4
Dependent Claim
13 words
The array of claim 1, wherein the first insulating glass layer is undoped.
Claim 5
Dependent Claim
24 words
The array of claim 3, wherein the first insulating glass layer is approximately 1000 Å thick over the upper surfaces of the gate electrodes.
Claim 6
Dependent Claim
25 words
The array of claim 1, wherein the passivation layer comprises a lower passivation layer of between about 500-2000 Å and an upper, thicker passivation layer.
Claim 7
Dependent Claim
20 words
The array of claim 5, wherein the lower passivation layer is characterized by ion damage corresponding to the code implantation.
Claim 8
Dependent Claim
22 words
The array of claim 5, wherein the lower passivation layer comprises one of silicon oxide, a doped silicon glass, or polysilicon glass.
Claim 9
Dependent Claim
14 words
The array of claim 5, wherein the upper, thicker passivation layer is a polyimide.
Claim 10
Dependent Claim
15 words
The array of claim 1, wherein unprogrammed cells in the memory array are normally ON.
Claim 11
Dependent Claim
25 words
The array of claim 1, wherein programmed cells in the memory array are implanted with a dopant annealed at a temperature of between 420°-520° C.
Claim 12
Dependent Claim
22 words
The array of claim 10, wherein programmed cells in the memory array are doped with a dopant of the first conductivity type.
Claim 13
Dependent Claim
21 words
The array of claim 11, wherein the programmed cells are implanted with boron annealed at a temperature of about 450° C.
Claim 14
Dependent Claim
19 words
The array of claim 1, wherein source/drain regions extend along each of the first, second and third gate electrodes.
Claim 15
Dependent Claim
27 words
The array of claim 13, wherein programmed cells have a code dopant in programmed cell channel regions extending from one source/drain region to an adjacent source/drain region.
Claim 16
Dependent Claim
18 words
The array of claim 1, wherein surfaces of the second doped insulating glass layers are smoothed by reflowing.
References Cited (Backward Citations)
US5081052A
Cited
JPH05121697A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |