Semiconductor device with increased on chip decoupling capacitance

Claim 2

A decoupling capacitor of a semiconductor device, comprising: a vertically-defined capacitor comprising a first layer of metallurgy separated by a dielectric layer: said first layer of metallurgy being located above a surface of said semiconductor device said dielectric layer being located on top of and aligned with said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of and aligned with said dielectric layer, relative to said surface of said semiconductor device; and wherein said vertically-defined capacitor is self-aligned about its perimeter with said first and second layers of metallurgy and of said dielectric layer being self-aligned and patterned together in one step.

Claim 3

A decoupling capacitor according to claim 1 wherein said first layer of metallurgy is disposed over a first lower level of connection of the semiconductor device for electrical coupling thereto.

Claim 4

A decoupling capacitor according to claim 1 wherein the two layers of metallurgy have a given area providing the capacitance for the decoupling capacitor in accordance with the thickness and dielectric value of the dielectric layer.

Claim 5

A decoupling capacitor according to claim 1 wherein the dielectric layer is one of an oxide or nitride material.

Claim 6

A decoupling capacitor of a semiconductor device, comprising: a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer; said first layer of metallurgy being located on a surface of said semiconductor device; said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device; portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being co-aligned and patterned together in one step; wherein said first layer of metallurgy is disposed over a first lower level of connection of the semiconductor device for electrical coupling thereto; and wherein said second layer of metallurgy is electrically coupled to a second lower level of connection of the semiconductor device via a third metallurgy layer disposed over the second lower level connection, the third metallurgy layer and second lower level of connection being adjacent to said first and second layers of metallurgy.

Claim 7

A decoupling capacitor of a semiconductor device, comprising: a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer; said first layer of metallurgy being located on a surface of said semiconductor device; said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device; portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being co-aligned and patterned together in one step; wherein said first layer of metallurgy is disposed over a first lower level of connection of the semiconductor device for electrical coupling thereto; and wherein said second layer of metallurgy is electrically coupled to a second lower level of connection of the semiconductor device via a third metallurgy layer disposed over the second lower level connection, the third metallurgy layer and second lower level of connection being adjacent to said first and second layers of metallurgy.

Claim 8

A decoupling capacitor according to claim 5 wherein said metallurgy deposition comprises a C4 solder ball.

Claim 9

A decoupling capacitor of a semiconductor device, comprising: a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer; said first layer of metallurgy being located on a surface of said semiconductor device; said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device; portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being coaligned and patterned together in one step; and wherein said first and second layers of metallurgy have an opening disposed over a lower level of connection of the semiconductor device and said second layer of the two layers of metallurgy is electrically coupled to the lower level of connection by way of metallurgy filling the opening.

Claim 10

A decoupling capacitor of a semiconductor device, comprising: a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer; said first layer of metallurgy being located on a surface of said semiconductor device; said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device; portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being coaligned and patterned together in one step; and wherein said first and second layers of metallurgy have an opening disposed over a lower level of connection of the semiconductor device and said second layer of the two layers of metallurgy is electrically coupled to the lower level of connection by way of metallurgy filling the opening.

Claim 11

A decoupling capacitor according to claim 7 wherein said first layer of the two layers of metallurgy is insulated from the metallurgy filling the opening by way of an insulating passivation lining that lines an inside periphery of the opening in the two layers of metallurgy.

Claim 12

A decoupling capacitor of a semiconductor device, comprising: a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer; said first layer of metallurgy being located on a surface of said semiconductor device; said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device; portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being coaligned and patterned together in one step; and wherein said second layer of the two layers of metallurgy and the dielectric layer therebetween include an opening lined with insulating passivation material, metallurgy being deposited through the opening for establishing an electrical contact coupled to said first layer of the two layers of metallurgy.

Claim 13

A decoupling capacitor of a semiconductor device, comprising: a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer; said first layer of metallurgy being located on a surface of said semiconductor device; said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device; said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device; portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being coaligned and patterned together in one step; and wherein said second layer of the two layers of metallurgy and the dielectric layer therebetween include an opening lined with insulating passivation material, metallurgy being deposited through the opening for establishing an electrical contact coupled to said first layer of the two layers of metallurgy.

Claim 14

A decoupling capacitor according to claim 9 wherein said second layer of the two layers of metallurgy is electrically coupled to a second stud of the semiconductor device via a separate metallurgy layer disposed over the second stud adjacent the two layers of metallurgy, and a metallurgy deposition that electrically couples the separate metallurgy layer to said second layer of the two layers of metallurgy.