Patent US5668401A successfully refreshed from Google Patents.
US5668401A
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Chessboard pattern layout for scribe lines
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-08-27
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Granted: 1997-09-16
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Expires: 2016-08-27
Abstract
Abstract A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies, to flat scribe regions, has been reduced. The reduction in photoresist flowing has been accomplished by creating a chessboard pattern of raised insulator and metal features, in the scribe line region, thus reducing the differences in topography between the scribe line and chip regions. The areas between the raised mesas, in the scribe line regions, are used for laser or optical endpoint detection of RIE processes.
Inventors
- 👤 Ying Chen Chao
- 👤 Chih-Heng Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:21
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/11; G; G03; G03F; G03F7/00; G03F7/16; H10P76/00; H10P76/20; Y; Y10; Y10S; Y10S438/00; Y10S438/941
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
119 words
A scribe line structure, between semiconductor chips, on a semiconductor substrate, comprising: a chessboard pattern of raised insulator mesas, on said semiconductor substrate, on a first region of said semiconductor substrate, with the height of said insulator mesas between about 5000 to 15000 Angstroms, and with the separation between said insulator mesas, on said semiconductor substrate, between about 5 to 15 μM; a field oxide region, on a second region of said semiconductor substrate; and a chessboard pattern of raised metal mesas, on said field oxide regions, with the height of said metal mesas between about 4000 to 14000 Angstroms, and with the separation between said metal mesas, on said field oxide region, between about 5 to 15 uM.
Claim 2
Dependent Claim
119 words
A scribe line structure, between semiconductor chips, on a semiconductor substrate, comprising: a chessboard pattern of raised insulator mesas, on said semiconductor substrate, on a first region of said semiconductor substrate, with the height of said insulator mesas between about 5000 to 15000 Angstroms, and with the separation between said insulator mesas, on said semiconductor substrate, between about 5 to 15 μM; a field oxide region, on a second region of said semiconductor substrate; and a chessboard pattern of raised metal mesas, on said field oxide regions, with the height of said metal mesas between about 4000 to 14000 Angstroms, and with the separation between said metal mesas, on said field oxide region, between about 5 to 15 uM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |