Patent US5671201A successfully refreshed from Google Patents.
US5671201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulling-in circuit for PLL circuit, pulling-in method for PLL circuit, PLL circuit device and apparatus for reproducing optical disc
Assignee: Pioneer Corp
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Filing: 1996-10-29
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Granted: 1997-09-23
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Expires: 2016-10-29
Abstract
Abstract A PLL circuit, to which an input signal is inputted, is provided with: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of the voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to the control voltage generation circuit. A pulling-in circuit for the PLL circuit is provided with: a sweep range setting circuit for setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; a lock detector for detecting whether or not a pulling-in operation is completed in the PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and a sweep range control circuit for controlling the control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is supplied thereto.
Inventors
- 👤 Hiroshi Yokota
- 👤 Ryuichi Naito
- 👤 Hiroyuki Hirano
- 👤 Katsumi Ishii
- 👤 Shinichi Naohara
- 👤 Yoshifumi Tsukada
- 👤 Kanya Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:28
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; G; G11; G11B; G11B19/00; G11B19/20; G11B19/24; G11B19/247; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H03L7/085; H03L7/095; H03L7/12; G11B20/12; G11B20/1217; G11B20/1258; G11B7/00; G11B7/002; G11B7/0037
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
206 words
A pulling-in circuit for a PLL circuit to which an input signal is inputted, said PLL circuit comprising: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of said voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to said control voltage generation circuit, said pulling-in circuit comprising: a sweep range setting circuit for setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; a lock detector for detecting whether or not a pulling-in operation is completed in said PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and a sweep range control circuit for controlling said control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is supplied thereto.
Claim 2
Dependent Claim
206 words
A pulling-in circuit for a PLL circuit to which an input signal is inputted, said PLL circuit comprising: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of said voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to said control voltage generation circuit, said pulling-in circuit comprising: a sweep range setting circuit for setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; a lock detector for detecting whether or not a pulling-in operation is completed in said PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and a sweep range control circuit for controlling said control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is supplied thereto.
Claim 3
Dependent Claim
60 words
A pulling-in circuit according to claim 1, in which said central frequency setting circuit sets the central frequency by adding a central frequency voltage corresponding to the central frequency onto the control voltage, wherein said sweep range control circuit controls said control signal generation circuit to sweep the control voltage through a voltage range corresponding to the set sweep range.
Claim 4
Dependent Claim
146 words
A pulling-in circuit according to claim 2, in which said control signal generation circuit comprises: a phase comparator for comparing the phases of the input and output signals to output a phase difference voltage; a loop filter for amplifying the phase difference voltage to output an amplified voltage which is swept through the voltage range by said sweep range control circuit; and an adder for adding the central frequency voltage onto the amplified voltage to output the control voltage, wherein said sweep range control circuit comprises: a direct voltage applying circuit for selectively applying one of two direct voltages, which have levels different from each other, to an input of said loop filter; and a switching circuit for switching the applied one of two direct voltages to another when the control voltage reaches each of an upper limit and a lower limit of the voltage range.
Claim 5
Dependent Claim
59 words
A pulling-in circuit according to claim 1, wherein said sweep range setting circuit comprises: an upper limit setting circuit for setting an upper limit value of the sweep range on the basis of the central frequency; and a lower limit setting circuit for setting a lower limit value of the sweep range on the basis of the central frequency.
Claim 6
Dependent Claim
61 words
A pulling-in circuit according to claim 2, wherein said sweep range setting circuit comprises: an upper limit setting circuit for setting an upper limit voltage of the voltage range on the basis of the central frequency voltage; and a lower limit setting circuit for setting a lower limit voltage of the voltage range on the basis of the central frequency voltage.
Claim 7
Dependent Claim
73 words
A pulling-in circuit according to claim 5, wherein said upper limit setting circuit sets the upper limit voltage by adding a result of multiplying the central frequency voltage by a first proportional coefficient P1 (P1>0) onto the central frequency voltage; and said lower limit setting circuit sets the lower limit voltage by subtracting a result of multiplying the central frequency voltage by a second proportional coefficient P2 (P2>0) from the central frequency voltage.
Claim 8
Dependent Claim
192 words
A pulling-in method for a PLL circuit to which an input signal is inputted, said PLL circuit comprising: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of said voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to said control voltage generation circuit, said pulling-in method comprising the steps of: setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; detecting whether or not a pulling-in operation is completed in said PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and controlling said control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is outputted.
Claim 9
Dependent Claim
192 words
A pulling-in method for a PLL circuit to which an input signal is inputted, said PLL circuit comprising: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of said voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to said control voltage generation circuit, said pulling-in method comprising the steps of: setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; detecting whether or not a pulling-in operation is completed in said PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and controlling said control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is outputted.
Claim 10
Dependent Claim
62 words
A pulling-in method according to claim 7, in which said central frequency setting circuit sets the central frequency by adding a central frequency voltage corresponding to the central frequency onto the control voltage, wherein said controlling step comprises the step of controlling said control signal generation circuit to sweep the control voltage through a voltage range corresponding to the set sweep range.
Claim 11
Dependent Claim
137 words
A pulling-in method according to claim 8, in which said control signal generation circuit comprises: a phase comparator for comparing the phases of the input and output signals to output a phase difference voltage; a loop filter for amplifying the phase difference voltage to output an amplified voltage which is swept through the voltage range by said sweep range control circuit; and an adder for adding the central frequency voltage onto the amplified voltage to output the control voltage, wherein said controlling step comprises the steps of: selectively applying one of two direct voltages, which have levels different from each other, to an input of said loop filter; and switching the applied one of two direct voltages to another when the control voltage reaches each of an upper limit and a lower limit of the voltage range.
Claim 12
Dependent Claim
50 words
A pulling-in method according to claim 7, wherein said sweep range setting step comprises the steps of: setting an upper limit value of the sweep range on the basis of the central frequency; and setting a lower limit value of the sweep range on the basis of the central frequency.
Claim 13
Dependent Claim
52 words
A pulling-in method according to claim 8, wherein said sweep range setting step comprises the steps of: setting an upper limit voltage of the voltage range on the basis of the central frequency voltage; and setting a lower limit voltage of the voltage range on the basis of the central frequency voltage.
Claim 14
Dependent Claim
81 words
A pulling-in method according to claim 11, wherein said upper limit setting step comprises the step of setting the upper limit voltage by adding a result of multiplying the central frequency voltage by a first proportional coefficient P1 (P1>0) onto the central frequency voltage; and said lower limit setting step comprises the step of setting the lower limit voltage by subtracting a result of multiplying the central frequency voltage by a second proportional coefficient P2 (P2>0) from the central frequency voltage.
Claim 15
Dependent Claim
211 words
A PLL circuit device comprising a PLL circuit, to which an input signal is inputted, and a pulling-in circuit, said PLL circuit comprising: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of said voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to said control voltage generation circuit, said pulling-in circuit comprising: a sweep range setting circuit for setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; a lock detector for detecting whether or not a pulling-in operation is completed in said PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and a sweep range control circuit for controlling said control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is supplied thereto.
Claim 16
Dependent Claim
211 words
A PLL circuit device comprising a PLL circuit, to which an input signal is inputted, and a pulling-in circuit, said PLL circuit comprising: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of said voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to said control voltage generation circuit, said pulling-in circuit comprising: a sweep range setting circuit for setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; a lock detector for detecting whether or not a pulling-in operation is completed in said PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and a sweep range control circuit for controlling said control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is supplied thereto.
Claim 17
Dependent Claim
60 words
A PLL circuit device according to claim 13, wherein said central frequency setting circuit sets the central frequency by adding a central frequency voltage corresponding to the central frequency onto the control voltage, and said sweep range control circuit controls said control signal generation circuit to sweep the control voltage through a voltage range corresponding to the set sweep range.
Claim 18
Dependent Claim
79 words
A PLL circuit device according to claim 13, wherein said control signal generation circuit comprises: a phase comparator for comparing the phases of the input and output signals to output a phase difference voltage; a loop filter for amplifying the phase difference voltage to output an amplified voltage which is swept through the voltage range by said sweep range control circuit; and an adder for adding the central frequency voltage onto the amplified voltage to output the control voltage.
Claim 19
Dependent Claim
75 words
A PLL circuit device according to claim 15, wherein said sweep range control circuit comprises: a direct voltage applying circuit for selectively applying one of two direct voltages, which have levels different from each other, to an input of said loop filter; and a switching circuit for switching the applied one of two direct voltages to another when the control voltage reaches each of an upper limit and a lower limit of the voltage range.
References Cited (Backward Citations)
US5469417A
Cited
US5553043A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |