US5684304A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Structure for testing integrated circuits
Assignee: ST Ericsson SA
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Filing: 1994-12-20
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Granted: 1997-11-04
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Expires: 2014-12-20
Abstract
Abstract An integrated circuit has at least one access pad connected to an element of an internal circuit through a capacitor including two opposed conductive layers insulated one from the other. The lower conductive layer portion is connected to the pad and the upper conductive layer portion is connected to the element. Thus, the upper conductive layer portion forms a d.c. current testing pad.
Inventors
- 👤 Nicholas William Smears
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:05
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10W; H10W72/00; H10W72/90; H10W72/931; H10W72/932; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
173 words
An integrated circuit having at least one access pad connected to an element of an internal circuit through a capacitor including lower conductive plate occupying a capacitor area defined thereby; an upper conductive plate occupying the capacitor area; a first insulation layer disposed between the lower conductive plate and the upper conductive plate; a second insulation layer disposed on the upper conductive plate and having at least one via defined therein; and a conductive contact layer disposed on the second insulation layer, occupying the capacitor area and connected to the upper conducting plate through the via defined in the second insulation layer; and wherein the lower conductive plate is connected to the pad and the upper conductive plate is connected to said element, wherein the conductive contact layer forms a test pad, and wherein the lower conductive plate is made of polycrystalline silicon and wherein the upper conductive plate is further connected to a diffused region beneath the lower conductive plate, the diffused region connected to a portion of a first metallization level.
Claim 2
Dependent Claim
173 words
An integrated circuit having at least one access pad connected to an element of an internal circuit through a capacitor including lower conductive plate occupying a capacitor area defined thereby; an upper conductive plate occupying the capacitor area; a first insulation layer disposed between the lower conductive plate and the upper conductive plate; a second insulation layer disposed on the upper conductive plate and having at least one via defined therein; and a conductive contact layer disposed on the second insulation layer, occupying the capacitor area and connected to the upper conducting plate through the via defined in the second insulation layer; and wherein the lower conductive plate is connected to the pad and the upper conductive plate is connected to said element, wherein the conductive contact layer forms a test pad, and wherein the lower conductive plate is made of polycrystalline silicon and wherein the upper conductive plate is further connected to a diffused region beneath the lower conductive plate, the diffused region connected to a portion of a first metallization level.
Claim 3
Dependent Claim
30 words
The integrated circuit of claim 1, wherein the portion of the first metallization level is coated with a portion of a conductive layer of a second metallization level connected thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |