US5687339A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pre-reading and pre-decoding of instructions of a microprocessor within single cycle
Assignee: Elan Microelectronics Corp
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Filing: 1995-09-14
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Granted: 1997-11-11
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Expires: 2015-09-14
Abstract
Abstract The present invention relates to a method of pre-reading and pre-decoding of instructions of a microprocessor, which allows each of all instructions to be executed within a single cycle without being influenced by the instructions such as jump, etc. This is achieved mainly by, at the same time that an instruction is executed, pre-reading next two instructions and deciding if the first one of the next two instructions is a call, jump or conditional instruction, in order to change the value of the program counter of the microprocessor before the completion of the execution of said instruction, thereby eliminating the time-consuming phenomenon caused by said change of the value of the program counter and rasing the processing speed in the microprocessor. A structure for the pre-reading of the next two instructions is also disclosed in the present invention.
Inventors
- 👤 Jyh-Guo Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3802; G06F9/3804
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
225 words
A method of pre-reading and pre-decoding of instructions of a microprocessor, the method comprising: a) pre-reading the next two instructions of a currently executed instruction, said pre-read next two instructions being stored in an odd memory bus and an even memory bus, respectively; b) pre-decoding the first one of said pre-read next two instructions, thereby deciding if the pre-decoded first instruction is a jump, call/return, conditional or ordinary instruction; and c) setting the value of the program counter of the microprocessor to a proper one based on said decision before a next instruction is executed, wherein when said pre-decoded first instruction is identified as a conditional instruction, said pre-read instructions stored in either said odd or even memory bus is retrieved and executed based on the operation result of the condition; when said pre-decoded first instruction is identified as a jump or call/return instruction, the value of the program counter is set to the address given in said jump or call/return instruction, and at the same time the instructions at next two addresses of said set address are pre-read and respectively stored in said odd and even memory buses, and when said jump or call/return instruction is executed, said jump or call/return instruction is replaced by a NOP (no operation) instruction, such that each of said instructions can be executed within a single clock cycle.
Claim 2
Independent Claim
225 words
A method of pre-reading and pre-decoding of instructions of a microprocessor, the method comprising: a) pre-reading the next two instructions of a currently executed instruction, said pre-read next two instructions being stored in an odd memory bus and an even memory bus, respectively; b) pre-decoding the first one of said pre-read next two instructions, thereby deciding if the pre-decoded first instruction is a jump, call/return, conditional or ordinary instruction; and c) setting the value of the program counter of the microprocessor to a proper one based on said decision before a next instruction is executed, wherein when said pre-decoded first instruction is identified as a conditional instruction, said pre-read instructions stored in either said odd or even memory bus is retrieved and executed based on the operation result of the condition; when said pre-decoded first instruction is identified as a jump or call/return instruction, the value of the program counter is set to the address given in said jump or call/return instruction, and at the same time the instructions at next two addresses of said set address are pre-read and respectively stored in said odd and even memory buses, and when said jump or call/return instruction is executed, said jump or call/return instruction is replaced by a NOP (no operation) instruction, such that each of said instructions can be executed within a single clock cycle.
Claim 3
Dependent Claim
159 words
The method according to claim 1, wherein the step of pre-decoding instructions further comprises: d) adding the value of the program counter by 1 if said pre-decoded first instruction is an ordinary instruction; e) adding the value of the program counter by 1 or 2 based on whether the operation condition is satisfied or not if said pre-decoded first instruction is a conditional instruction; f) storing the current value of the program counter or retrieving the original value of the program counter at first and then setting the program counter to be the value given in a call/return instruction if said pre-decoded first instruction is the call/return instruction; g) setting directly the value of the program counter to be a value given in a jump instruction if said pre-decoded first instruction is the jump instruction; and h) executing a next instruction and repeating said pre-decoding of instructions after each of said alterations of the value of the program counter.
Claim 4
Dependent Claim
103 words
A structure for pre-reading next two instructions of a currently executed instruction in a microprocessor, the structure comprising: a) an address increment for increasing an inputted address A 1 -A 11 by 1; b) two address selectors for respectively selecting an address from said inputted address and said increased address based on an address A 0 ; c) odd and even memories for respectively outputting a responding data based on one of said selected addresses; and d) a data selector for selecting a data from said outputted data based on an instruction selection line, thereby achieving said pre-reading of the next two instructions.
Claim 5
Dependent Claim
103 words
A structure for pre-reading next two instructions of a currently executed instruction in a microprocessor, the structure comprising: a) an address increment for increasing an inputted address A 1 -A 11 by 1; b) two address selectors for respectively selecting an address from said inputted address and said increased address based on an address A 0 ; c) odd and even memories for respectively outputting a responding data based on one of said selected addresses; and d) a data selector for selecting a data from said outputted data based on an instruction selection line, thereby achieving said pre-reading of the next two instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-10 | 2001-05-12 | 2001-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-10 | 2005-05-12 | 2005-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-10 | 2009-05-12 | 2009-11-11 | $7700.00 | Window Closed / Lapsed |