Semiconductor memory device having improved bit line distribution

Claim 2

A semiconductor memory comprising: a memory cell array including 2N (N≧2) bit line pairs arranged in columns, each of the bit line pairs coupled to a plurality of memory cells; a first sense amplifier array having N first sense amplifier circuits arranged in a first column at one side of the memory cell array, each of the first sense amplifier circuits coupled to one of the bit line pairs, thereby coupling the first sense amplifier array to N of the bit line pairs; a second sense amplifier array having N second sense amplifier circuits arranged in a second column at the opposite side of the memory cell array, each of the second sense amplifier circuits coupled to another of the bit line pairs, thereby coupling the second sense amplifier array to the other N of the bit line pairs; and a plurality of regions, each of the regions located between ends of M of the bit line pairs and one of the sense amplifier arrays, wherein a first signal line and a second signal line are shunted at one or more of the regions; wherein a first group of M (M≧2) adjacent bit line pairs is distributed to one of the sense amplifier arrays and a second group of M adjacent bit line pairs bordering the first group is distributed to the other sense amplifier array.

Claim 3

The semiconductor memory according to claim 1, wherein each of the sense amplifier circuits includes an equalizing circuit for equalizing the corresponding bit line pairs with an intermediate voltage, the equalizing circuits having first, second and third MOS transistors, the first signal line is a wiring for controlling the first, the second, and the third MOS transistors and is integral with gate electrodes thereof, and the second signal line is a bypass wiring for supplying a control signal to the first signal line.

Claim 4

The semiconductor memory according to claim 2, wherein the first signal line is constructed in a polysilicon layer, and the second signal line is constructed in a metal wiring layer.

Claim 5

The semiconductor memory according to claim 1, wherein each of the sense amplifier circuits includes an equalizing circuit for equalizing the corresponding bit line pairs with an intermediate voltage, the first signal line is a wiring for providing the intermediate voltage to the equalizing circuit, and the second signal line is a bypass wiring for supplying the intermediate voltage to first signal line.

Claim 6

The semiconductor memory according to claim 4, wherein the first signal line is constructed in an impurity diffusion layer, and the second signal line is constructed in a metal wiring layer.

Claim 7

The semiconductor memory according to claim 1, wherein M is two.

Claim 8

The semiconductor memory according to claim 1, wherein M is four.

Claim 9

A semiconductor memory comprising: a memory cell array including 2N (N≧2) bit line pairs arranged in columns, each of the bit line pairs coupled to a plurality of memory cells; a first sense amplifier array having N first sense amplifier circuits arranged in a first column at one side of the memory cell array, each of the first sense amplifier circuits coupled to one of the bit line pairs, thereby coupling the first sense amplifier array to N of the bit line pairs; and a second sense amplifier array having N second sense amplifier circuits arranged in a second column at the opposite side of the memory cell array, each of the second sense amplifier circuits coupled to another of the bit line pairs, thereby coupling the second sense amplifier array to the other N of the bit line pairs, wherein a first group of M (M≧2) adjacent bit line pairs is distributed to one of the sense amplifier arrays and a second group of M adjacent bit line pairs bordering the first group is distributed to the other sense amplifier array, and each of the bit line pairs is jogged at the end near its corresponding sense amplifier circuit to create regions for shunting a first signal line and a second signal line, and to allow the sense amplifier circuits to be arranged at regular intervals.

Claim 10

A semiconductor memory comprising: a memory cell array including 2N (N≧2) bit line pairs arranged in columns, each of the bit line pairs coupled to a plurality of memory cells; a first sense amplifier array having N first sense amplifier circuits arranged in a first column at one side of the memory cell array, each of the first sense amplifier circuits coupled to one of the bit line pairs, thereby coupling the first sense amplifier array to N of the bit line pairs; and a second sense amplifier array having N second sense amplifier circuits arranged in a second column at the opposite side of the memory cell array, each of the second sense amplifier circuits coupled to another of the bit line pairs, thereby coupling the second sense amplifier array to the other N of the bit line pairs, wherein a first group of M (M≧2) adjacent bit line pairs is distributed to one of the sense amplifier arrays and a second group of M adjacent bit line pairs bordering the first group is distributed to the other sense amplifier array, and each of the bit line pairs is jogged at the end near its corresponding sense amplifier circuit to create regions for shunting a first signal line and a second signal line, and to allow the sense amplifier circuits to be arranged at regular intervals.

Claim 11

A semiconductor memory comprising: first, second, third and fourth adjacent bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; and a fourth sense amplifier circuit connected to the right end of the fourth bit line pair, wherein the first sense amplifier is adjacent to the fourth sense amplifier, and the second sense amplifier is adjacent to the third sense amplifier.

Claim 12

A semiconductor memory comprising: first, second, third and fourth adjacent bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; and a fourth sense amplifier circuit connected to the right end of the fourth bit line pair, wherein the first sense amplifier is adjacent to the fourth sense amplifier, and the second sense amplifier is adjacent to the third sense amplifier.

Claim 13

A semiconductor memory comprising: first, second, third and fourth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the right end of the fourth bit line pair; and a shunt region for shunting wirings in different layers, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits.

Claim 14

A semiconductor memory comprising: first, second, third and fourth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the right end of the fourth bit line pair; and a shunt region for shunting wirings in different layers, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits.

Claim 15

The semiconductor memory according to claim 10, wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

Claim 16

A semiconductor memory comprising: first, second, third and fourth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the right end of the fourth bit line pair; a first equalizing signal line for providing a control signal for the MOS transistors, the first equalizing signal line being integral with gate electrodes of the MOS transistors; a second equalizing signal line for bypassing the control signal; and a shunt region for shunting the first equalizing signal line and the second equalizing signal line, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits, wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

Claim 17

A semiconductor memory comprising: first, second, third and fourth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the right end of the fourth bit line pair; a first equalizing signal line for providing a control signal for the MOS transistors, the first equalizing signal line being integral with gate electrodes of the MOS transistors; a second equalizing signal line for bypassing the control signal; and a shunt region for shunting the first equalizing signal line and the second equalizing signal line, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits, wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

Claim 18

The semiconductor memory according to claim 12, wherein the first equalizing signal line is constructed in a polysilicon layer, and the second equalizing signal line is constructed in a metal wiring layer.

Claim 19

A semiconductor memory comprising: first, second, third and fourth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the right end of the fourth bit line pair; a first intermediate voltage line for providing the intermediate voltage for source/drain electrodes of the MOS transistors; a second intermediate voltage line for bypassing the intermediate voltage; and a shunt region for shunting the first intermediate voltage line and the second intermediate voltage line, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits, wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

Claim 20

A semiconductor memory comprising: first, second, third and fourth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the right end of the fourth bit line pair; a first intermediate voltage line for providing the intermediate voltage for source/drain electrodes of the MOS transistors; a second intermediate voltage line for bypassing the intermediate voltage; and a shunt region for shunting the first intermediate voltage line and the second intermediate voltage line, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits, wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

Claim 21

The semiconductor memory according to claim 14, wherein the first intermediate voltage line is constructed in an impurity diffusion layer, and the second intermediate voltage line is constructed in a metal wiring layer.

Claim 22

A semiconductor memory comprising: first, second, third, fourth, fifth, and sixth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the left end of the fourth bit line pair; a fifth sense amplifier circuit connected to the left end of the fifth bit line pair; and a sixth sense amplifier circuit connected to the right end of the sixth bit line pair.

Claim 23

A semiconductor memory comprising: first, second, third, fourth, fifth, and sixth bit line pairs arranged in this order in parallel; a first sense amplifier circuit connected to the right end of the first bit line pair; a second sense amplifier circuit connected to the left end of the second bit line pair; a third sense amplifier circuit connected to the left end of the third bit line pair; a fourth sense amplifier circuit connected to the left end of the fourth bit line pair; a fifth sense amplifier circuit connected to the left end of the fifth bit line pair; and a sixth sense amplifier circuit connected to the right end of the sixth bit line pair.

Claim 24

The semiconductor memory according to claim 16, further comprising a shunt region for shunting wirings in different layers, the shunt region being bounded by the right ends of the second to the fifth bit line pairs and the first and the sixth sense amplifier circuits.

Claim 25

The semiconductor memory according to claim 16, wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

Claim 26

The semiconductor memory according to claim 18, further comprising: a first equalizing signal line for providing a control signal for the MOS transistors, the first equalizing signal line being integral with gate electrodes of the MOS transistors; a second equalizing signal line for bypassing the control signal; and a shunt region for shunting the first equalizing signal line and the second equalizing signal line, the shunt region being bounded by the right ends of the second to the fifth bit line pairs and the first and the sixth sense amplifier circuits.

Claim 27

The semiconductor memory according to claim 18, further comprising: a first intermediate voltage line for providing the intermediate voltage for source/drain electrodes of MOS transistors; a second intermediate voltage line for bypassing the intermediate voltage; and a shunt region for shunting the first intermediate voltage line and the second intermediate voltage line, the shunt region being bounded by the right ends of the second to the first bit line pairs and the first and the sixth sense amplifier circuits.