Patent EP0834843A2 successfully refreshed from Google Patents.
Patent US5693540A successfully refreshed from Google Patents.
US5693540A
Expired / Lapsed
US
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Method of fabricating integrated circuits
Assignee: Altera Corp
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Filing: 1996-05-31
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Granted: 1997-12-02
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Expires: 2016-05-31
Abstract
Abstract A method of fabricating integrated circuits is provided that allows new integrated circuits to be fabricated with reduced die areas and reduced power consumptions relative to old integrated circuits. The new circuits are interchangeable with the old integrated circuits, because the delay times for the data pathways through the new circuits are the same as the delay times for the data pathways through the old circuits. A family of new circuits, each of which is compatible with a corresponding one of a series of old circuits, can be fabricated using a common circuit layout. Each new circuit is associated with a parameter value that governs the delay time of a component in a data pathway through the circuit and ensures that the new circuit is compatible with the corresponding old circuit.
Inventors
- 👤 John E. Turner
- 👤 Kevin A. Norman
- 👤 Thomas Henry White
- 👤 Wilson Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:47
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/10; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
214 words
A method of fabricating integrated circuits in which a circuit design originally implemented using an old process to form a first integrated circuit is implemented using a new fabrication process to form a second integrated circuit, said second integrated circuit having a die area that is smaller than that of said first integrated circuit, said first and second integrated circuits each having a data input, a data output, and a plurality of components each occupying a respective die area, at least some of said components having an associated delay time and being connected between said data input and said data output to form a pathway having a total delay time, said method comprising the steps of: identifying a predetermined component on said first integrated circuit with a die area that can be reduced by fabricating said predetermined component with said new fabrication process; and fabricating said second integrated circuit including said predetermined component using said new fabrication process on said second integrated circuit, said predetermined component having a die area that is reduced relative to said die area of said predetermined component on said first integrated circuit, said total delay time of said pathway on said second integrated circuit being equal to said total delay time of said pathway on said first integrated circuit.
Claim 2
Independent Claim
214 words
A method of fabricating integrated circuits in which a circuit design originally implemented using an old process to form a first integrated circuit is implemented using a new fabrication process to form a second integrated circuit, said second integrated circuit having a die area that is smaller than that of said first integrated circuit, said first and second integrated circuits each having a data input, a data output, and a plurality of components each occupying a respective die area, at least some of said components having an associated delay time and being connected between said data input and said data output to form a pathway having a total delay time, said method comprising the steps of: identifying a predetermined component on said first integrated circuit with a die area that can be reduced by fabricating said predetermined component with said new fabrication process; and fabricating said second integrated circuit including said predetermined component using said new fabrication process on said second integrated circuit, said predetermined component having a die area that is reduced relative to said die area of said predetermined component on said first integrated circuit, said total delay time of said pathway on said second integrated circuit being equal to said total delay time of said pathway on said first integrated circuit.
Claim 3
Dependent Claim
78 words
The method defined in claim 1 wherein said predetermined component on said first integrated circuit with a die area that can be reduced is test circuits and pads, said step of fabricating said predetermined component using said new fabrication process comprising the step of fabricating said test circuits and pads on said second integrated circuit with a die area that is reduced relative to said die area of said test circuits and pads on said first integrated circuit.
Claim 4
Dependent Claim
133 words
The method defined in claim 1 wherein said predetermined component is one of the components in said pathway between said data input and said data output having one of said associated delay times, said step of fabricating said predetermined component comprising the step of fabricating said predetermined component using said new fabrication process on said second integrated circuit with an associated delay time that is reduced relative to said associated delay time of said predetermined component on said first integrated circuit, said method further comprising the step of fabricating at least one of said components in said pathway other than said predetermined component using said new fabrication process on said second integrated circuit with an associated delay time that is increased to compensate for the reduced associated delay time of said predetermined component.
Claim 5
Dependent Claim
106 words
The method defined in claim 3 wherein said predetermined component is EPROM array/sense amplifier circuitry, said EPROM array/sense amplifier circuitry having a die area and an associated delay time on said first integrated circuit, said step of fabricating said predetermined component comprising the step of fabricating said EPROM array/sense amplifier circuitry using said new process on said second integrated circuit with a die area that is reduced relative to said die area of said EPROM array/sense amplifier circuitry on said first integrated circuit and with a reduced associated delay time relative to said associated delay time of said EPROM array/sense amplifier on said first integrated circuit.
Claim 6
Dependent Claim
119 words
The method defined in claim 4 wherein said at least one component in said pathway other than said predetermined component includes input buffer circuitry and word line driver circuitry, each having a die area and an associated delay time on said first integrated circuit, said step of fabricating said at least one component in said pathway other than said predetermined component comprising the step of fabricating said input buffer circuitry and said word line driver circuitry using said new fabrication process on said second integrated circuit such that said associated delay times of said input buffer circuitry and said word line driver circuitry are increased to compensate for said reduced associated delay time of said EPROM array/sense amplifier circuitry.
Claim 7
Dependent Claim
108 words
The method defined in claim 5 wherein said first and second integrated circuits each further comprise feedback circuitry having an associated delay time, said feedback circuitry connecting said EPROM array/sense amplifier circuitry to said word line driver circuitry, said method further comprising the step of fabricating said feedback circuitry on said second integrated circuit with said new fabrication process, said associated delay time of said feedback circuitry on said second integrated circuit being increased relative to said associated delay time of said feedback circuitry on said first integrated circuit so that said feedback circuitry is synchronized with said EPROM array/sense amplifier circuitry and said word line driver circuitry.
Claim 8
Independent Claim
236 words
A method of fabricating integrated circuits in which a circuit design originally implemented using a plurality of old fabrication processes to form a plurality of old circuits is implemented using a new fabrication process to form a family of new circuits, said new fabrication process allowing said new circuits to be fabricated with smaller die areas than said old circuits, each new circuit being interchangeable with a corresponding one of said old circuits and having a smaller die area than said corresponding one of said old circuits, said old circuits and said new circuits each having a data input, a data output, and a plurality of components, said components having associated delay times and being connected between said data input and said data output to form a pathway having a total delay time, said method comprising the steps of: creating a common layout from which said family of new circuits can be constructed and which has a component containing a structure that has an associated parameter; generating a family of parameter values for said parameter, such that for each new circuit one of said parameter values governs the dimensions of said structure in said component, said dimensions governing said associated delay time of said component; and fabricating said family of new circuits using said new process, said total delay time of each new circuit being equal to said total delay time of said corresponding old circuit.
Claim 9
Independent Claim
236 words
A method of fabricating integrated circuits in which a circuit design originally implemented using a plurality of old fabrication processes to form a plurality of old circuits is implemented using a new fabrication process to form a family of new circuits, said new fabrication process allowing said new circuits to be fabricated with smaller die areas than said old circuits, each new circuit being interchangeable with a corresponding one of said old circuits and having a smaller die area than said corresponding one of said old circuits, said old circuits and said new circuits each having a data input, a data output, and a plurality of components, said components having associated delay times and being connected between said data input and said data output to form a pathway having a total delay time, said method comprising the steps of: creating a common layout from which said family of new circuits can be constructed and which has a component containing a structure that has an associated parameter; generating a family of parameter values for said parameter, such that for each new circuit one of said parameter values governs the dimensions of said structure in said component, said dimensions governing said associated delay time of said component; and fabricating said family of new circuits using said new process, said total delay time of each new circuit being equal to said total delay time of said corresponding old circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |