US5696534A
Expired / Lapsed
US
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Time multiplexing pixel frame buffer video output
Assignee: Sun Microsystems Inc
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Filing: 1995-03-21
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Granted: 1997-12-09
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Expires: 2015-03-21
Abstract
Abstract A method and for multiplexing pixel data from a frame buffer to a RAMDAC to reduce the number of pins required. For many graphics operations optimal performance is achieved by storing an entire 32-bit pixel in a single RAM chip. When displaying video data from a frame buffer, pixels must be read out serially from the frame buffer at real-time speeds. A frame buffer memory with 16 pins for serial video output is used. An entire 32-bit pixel is stored in a single RAM chip. For a 32-bit pixel containing four byte (8-bit) quantities designated X, B, G and R, on the first clock cycle, the X and B bytes are made available on the 16 pins of the frame buffer. On the next clock cycle, the G and R bytes are made available. Thus, over two cycles the entire 32-bit pixel is output from the frame buffer to a RAMDAC which samples the X and B bytes on 16 input pins. The RAMDAC stores these X and B bytes in an internal register. On the next clock cycle it samples the G and R bytes. The DAC then reassembles the X, B, G and R bytes into a single 32-bit pixel for conversion into video. In this manner, 32-bit pixels are communicated across a 16-bit pixel data bus.
Inventors
- 👤 Michael G. Lavelle
- 👤 Alex N. Koltzoff
- 👤 David C. Kehlet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:34
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/395
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
136 words
An apparatus for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising: a) interleaving format circuits for coupling to a frame buffer and receiving interleaved pixel data having the form n/m:1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>m>1; b) logic circuits coupled to the interleaving format circuits for processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC, wherein said interleaving format circuits include circuits which undo the interleaving performed by said frame buffer and assemble said pixel data as received from said frame buffer into corresponding sets of pixel data.
Claim 2
Independent Claim
136 words
An apparatus for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising: a) interleaving format circuits for coupling to a frame buffer and receiving interleaved pixel data having the form n/m:1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>m>1; b) logic circuits coupled to the interleaving format circuits for processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC, wherein said interleaving format circuits include circuits which undo the interleaving performed by said frame buffer and assemble said pixel data as received from said frame buffer into corresponding sets of pixel data.
Claim 3
Dependent Claim
45 words
The apparatus defined by claim 1 wherein said undoing and assembling circuits comprises sets of registers and multiplexors which are coupled together to form a plurality of sub-blocks which cooperatively operate so that each produces a complete pixel formed by a predetermined number of bits.
Claim 4
Dependent Claim
24 words
The apparatus defined by claim 2 wherein predetermined ones of said sub-blocks receive signals which define the interleaving format performed by said frame buffer.
Claim 5
Dependent Claim
30 words
The apparatus defined by claim 1 wherein the interleaved pixel data is in one of: 4/2:1 single buffered interleaving format; 4/2:1 double buffered interleaving format; 8/2:1 single buffered interleaving format.
Claim 6
Dependent Claim
108 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PA(15:00) of said pixel data; a second register which receives bits PA(31:16) of said pixel data; a third register which receives bits PA(15:00) of said pixel data; a fourth register coupled to said first register; a multiplexor coupled to said second and third registers; a fifth register coupled to said fourth register and said multiplexor.
Claim 7
Dependent Claim
105 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PA(31:24) of said pixel data; a second register which receives bits PA(63:32) of said pixel data; a third register which receives bits PA(31:24) of said pixel data; a fourth register coupled to said first register; a multiplexor coupled to said second, third and fourth registers; a fifth register coupled to said multiplexor.
Claim 8
Dependent Claim
105 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PA(47:32) of said pixel data; a second register which receives bits PB(31:00) of said pixel data; a third register which receives bits PA(47:32) of said pixel data; a fourth register coupled to said first register; a multiplexor coupled to said second, third and fourth registers; a fifth register coupled to said multiplexor.
Claim 9
Dependent Claim
105 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PA(63:48) of said pixel data; a second register which receives bits PB(63:32) of said pixel data; a third register which receives bits PA(63:48) of said pixel data; a fourth register coupled to said first register; a multiplexor coupled to said second, third and fourth registers; a fifth register coupled to said multiplexor.
Claim 10
Dependent Claim
89 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PB(15:00) of said pixel data; a second register which receives bits PB(15:00) of said pixel data; a third register coupled to said first register; a fourth register coupled to said second register and said third register.
Claim 11
Dependent Claim
89 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PB(31:16) of said pixel data; a second register which receives bits PB(31:16) of said pixel data; a third register coupled to said first register; a fourth register coupled to said second register and said third register.
Claim 12
Dependent Claim
89 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PB(47:32) of said pixel data; a second register which receives bits PB(47:32) of said pixel data; a third register coupled to said first register; a fourth register coupled to said second register and said third register.
Claim 13
Dependent Claim
89 words
The apparatus defined by claim 2 wherein said received pixel data comprises 128 pixel bits divided into two sets containing 64 bits each, the bits in said first set being designated PA(63:00), the bits in said second set being designated PB(63:00), wherein one of said sub-blocks comprises: a first register which receives bits PB(63:48) of said pixel data; a second register which receives bits PB(63:48) of said pixel data; a third register coupled to said first register; a fourth register coupled to said second register and said third register.
Claim 14
Dependent Claim
86 words
The apparatus defined by claim 1 wherein said processing logic circuits comprise: a first multiplexor coupled to said interleaving format circuits; a pipeline register coupled to said first multiplexor and said interleaving format circuits; a second multiplexor coupled to pipeline register; a shift register coupled to said pipeline register and said second multiplexor. register is coupled to pipeline register so that fifth through eighth sets of pixel data input to said shift register are fifth through eighth sets of pixel data output from said pipeline register.
Claim 15
Dependent Claim
105 words
The apparatus defined by claim 13 wherein said interleaving format circuits assemble said pixel data as received from said frame buffer into corresponding sets of pixel data and said first multiplexor is coupled to said interleaving format circuits so that a first set of said pixel data is a first selectable input to said first multiplexor; a second set of said pixel data is a second selectable input to said first multiplexor; a third set of said pixel data is a third selectable input to said first multiplexor; and a fourth set of said pixel data is a fourth selectable input to said first multiplexor.
Claim 16
Dependent Claim
102 words
The apparatus defined by claim 14 wherein said pipeline register is coupled to said first multiplexor to receive first and second selected outputs from said first multiplexor as first and second inputs and is coupled to said interleaving format circuits to receive: as a third input, said third set of pixel data; as a fourth input, said fourth set of pixel data; as a fifth input, a fifth set of pixel data; as a sixth input, a sixth set of pixel data; as a seventh input, a seventh set of pixel data; as an eighth input, an eighth set of pixel data.
Claim 17
Dependent Claim
55 words
The apparatus defined by claim 15 wherein said second multiplexor is coupled to said pipeline register to receive as a first selectable input, said first through fourth sets of pixel data output from said pipeline register, and as a second selectable input, said fifth through eighth sets of pixel data output from said pipeline register.
Claim 18
Dependent Claim
73 words
The apparatus defined by claim 16 wherein said shift register is coupled to said multiplexor so that first through fourth sets of pixel data input to said shift register are a selected output of said second multiplexor, and said shift register is coupled to pipeline register so that fifth through eighth sets of pixel data input to said shift register are fifth through eighth sets of pixel data output from said pipeline register.
Claim 19
Independent Claim
131 words
A method for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising the steps of: a) undoing the interleaving performed by said frame buffer and assembling said pixel data as received from said frame buffer into corresponding sets of pixel data, said pixel data having the form n/m:1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>m>; b) processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC, wherein said undoing and assembling produces a plurality of complete pixel sets, each formed by a predetermined number of bits.
Claim 20
Independent Claim
131 words
A method for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising the steps of: a) undoing the interleaving performed by said frame buffer and assembling said pixel data as received from said frame buffer into corresponding sets of pixel data, said pixel data having the form n/m:1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>m>; b) processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC, wherein said undoing and assembling produces a plurality of complete pixel sets, each formed by a predetermined number of bits.
Claim 21
Dependent Claim
21 words
The method defined by claim 18 wherein said undoing and assembling step produces first through eighth sets of complete pixel data.
Claim 22
Dependent Claim
118 words
The method defined by claim 19 wherein said processing step comprises the steps of: first selecting first and second sets of pixel data from among said first through fourth sets of pixel data; passing said first and second sets of selected pixel data and said third through eighth sets of pixel data; second selecting first through fourth sets of said pixel data from among said first through fourth sets of said pixel data on the one hand and from among said fifth through eighth sets of said pixel data on the other hand; passing said second selected sets of pixel data as first through fourth sets of pixel data and said fifth through eighth sets of pixel data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |