US5696716A
Expired / Lapsed
US
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Programmable memory element
Assignee: STMicroelectronics SRL
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Filing: 1997-02-04
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Granted: 1997-12-09
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Expires: 2017-02-04
Abstract
Abstract A non-volatile memory element with dual programmable cells and associated read circuit, which comprises a circuit of the bistable type connected between the two memory cells, to which it is coupled through first and second switching circuit elements. Such switching elements enable a single initial write step by one of the two memory cells only, and thereafter, enable connection of the clear cell and the programmed cell to the bistable circuit.
Inventors
- 👤 Paolo Rolandi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:27
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C14/00; G11C16/06; G11C16/26; G11C29/00; G11C29/70; G11C29/78
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
133 words
A memory element of the programmable type with a read circuit featuring zero consumption in the quiescent state, the memory element comprising: a bistable circuit having at least first and second terminals; first and second switching circuit elements; first and second non-volatile memory transistors each having a source and a drain, the bistable circuit being connected between said transistors with the first and second terminals and coupled thereto through the first and second switching circuit element, respectively, said switching circuit elements operative to connect the first and second memory transistors to programming circuit means during a write step, said switching circuit elements being responsive to a change in a supply voltage to automatically connect the drains of the first and second memory transistors to the bistable circuit regardless of a power-on reset signal.
Claim 2
Dependent Claim
133 words
A memory element of the programmable type with a read circuit featuring zero consumption in the quiescent state, the memory element comprising: a bistable circuit having at least first and second terminals; first and second switching circuit elements; first and second non-volatile memory transistors each having a source and a drain, the bistable circuit being connected between said transistors with the first and second terminals and coupled thereto through the first and second switching circuit element, respectively, said switching circuit elements operative to connect the first and second memory transistors to programming circuit means during a write step, said switching circuit elements being responsive to a change in a supply voltage to automatically connect the drains of the first and second memory transistors to the bistable circuit regardless of a power-on reset signal.
Claim 3
Dependent Claim
28 words
A memory element according to claim 1, characterized in that at least one of said first and second memory transistors is in an unprogrammed state after the write-step.
Claim 4
Dependent Claim
20 words
A memory element according to claim 1, characterized in that the first and second switching circuit elements are electronic switches.
Claim 5
Dependent Claim
18 words
A memory element according to claim 1, characterized in that the electronic switches each comprise mutually complementary transistors.
Claim 6
Dependent Claim
23 words
A memory element according to claim 1, characterized in that the first and second non-volatile memory transistors are of the field-effect transistor type.
Claim 7
Dependent Claim
41 words
A memory element according to claim 1, characterized in that the bistable circuit comprises first and second inverters connected in a loop, the first and second terminals of the bistable circuit being circuit linking nodes between the first and second inverters.
Claim 8
Dependent Claim
23 words
A memory element as claimed in claim 1 wherein the memory element holds a portion of a redundancy address in a redundancy circuit.
Claim 9
Dependent Claim
111 words
A memory element that can be programmed with a programming circuit, comprising: a bistable circuit having first and second terminals and operable to dissipate substantially zero power in a quiescent state; first and second nonvolatile memory transistors each having a source and a drain; and first and second switching elements interposed between said first and second memory transistors and said first and second terminals respectively, said switching elements operable to couple said memory transistors to said programming circuit during a write and said switching elements responsive to a rise in a supply voltage to automatically couple said drains of said memory transistors to said terminals regardless of a power-on reset signal.
Claim 10
Dependent Claim
111 words
A memory element that can be programmed with a programming circuit, comprising: a bistable circuit having first and second terminals and operable to dissipate substantially zero power in a quiescent state; first and second nonvolatile memory transistors each having a source and a drain; and first and second switching elements interposed between said first and second memory transistors and said first and second terminals respectively, said switching elements operable to couple said memory transistors to said programming circuit during a write and said switching elements responsive to a rise in a supply voltage to automatically couple said drains of said memory transistors to said terminals regardless of a power-on reset signal.
Claim 11
Dependent Claim
36 words
The memory element of claim 8 wherein each of said switching elements comprises a pair of complementary transistors coupled in parallel and interposed between a respective memory transistor and a respective terminal of said bistable circuit.
Claim 12
Dependent Claim
19 words
The memory element of claim 8 wherein said memory transistors each comprise a field-effect transistor having a floating gate.
Claim 13
Dependent Claim
54 words
The memory element of claim 8 wherein said bistable circuit comprises: a first branch having an input terminal coupled to said second terminal and an output terminal coupled to said first terminal; and a second branch having an input terminal coupled to said first terminal and an output terminal coupled to said second terminal.
Claim 14
Dependent Claim
39 words
The memory element of claim 11 wherein each of said branches comprises a pair of transistors each having a gate coupled to said input terminal of said branch and a drain coupled to said output terminal of said branch.
Claim 15
Dependent Claim
95 words
In an integrated circuit, a memory device for automatically reading the memory transistors in response to a change in a supply voltage, the memory device comprising: a latch having first and second inputs; first and second nonvolatile memory transistors; and a first switch connected between the first memory transistor and the first input; a second switch connected between the second memory transistor and the second input, the switches being responsive to the change in the supply voltage to automatically connect the memory transistors to the first and second inputs regardless of a power-on reset signal.
Claim 16
Dependent Claim
95 words
In an integrated circuit, a memory device for automatically reading the memory transistors in response to a change in a supply voltage, the memory device comprising: a latch having first and second inputs; first and second nonvolatile memory transistors; and a first switch connected between the first memory transistor and the first input; a second switch connected between the second memory transistor and the second input, the switches being responsive to the change in the supply voltage to automatically connect the memory transistors to the first and second inputs regardless of a power-on reset signal.
Claim 17
Dependent Claim
23 words
The memory device of claim 13 wherein the switches connect the memory transistors to a programming circuit during programming of the memory transistors.
Claim 18
Dependent Claim
26 words
The memory device of claim 13 wherein the switches automatically connect the memory transistors to the first and second inputs upon power-on of the integrated circuit.
Claim 19
Dependent Claim
32 words
The memory device of claim 13 wherein each switch includes a pair of complementary transistors connected in parallel and interposed between a respective memory transistor and a respective input of the latch.
Claim 20
Dependent Claim
111 words
In an integrated circuit, a memory device for automatically reading the memory transistors regardless of a power-on reset signal, the memory device comprising: a bistable circuit having first and second inputs; first and second nonvolatile memory transistors; a first switch connected between the first memory transistor and the first input of the bistable circuit; and a second switch connected between the second memory transistor and the second input of the bistable circuit, the switches being responsive to a rise in the supply voltage upon power-on of the integrated circuit to automatically connect the memory transistors to the first and second inputs of the bistable circuit regardless of the power-on reset signal.
Claim 21
Dependent Claim
111 words
In an integrated circuit, a memory device for automatically reading the memory transistors regardless of a power-on reset signal, the memory device comprising: a bistable circuit having first and second inputs; first and second nonvolatile memory transistors; a first switch connected between the first memory transistor and the first input of the bistable circuit; and a second switch connected between the second memory transistor and the second input of the bistable circuit, the switches being responsive to a rise in the supply voltage upon power-on of the integrated circuit to automatically connect the memory transistors to the first and second inputs of the bistable circuit regardless of the power-on reset signal.
Claim 22
Dependent Claim
20 words
The memory device of claim, 13 wherein each of the memory transistors has a control terminal receiving the supply voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |