JTAG interface system for communicating with compliant and non-compliant JTAG devices

Claim 2

A control system for non-compliant JTAG devices comprising: (a) a non-compliant JTAG device which is normally incapable of following the standard JTAG protocol states during the Test Mode Select sequence of states; (b) means to control the operation of said non-compliant device to operate compatibly with the JTAG protocol, said means including a specialized Test Access Port (TAP) controller.

Claim 3

The system of claim 1 wherein said non-compliant device includes: (a) an integrated circuit chip holding a microprocessor and cache unit; (b) means to circulate input test data through said microprocessor and cache unit for readout and diagnosis of said microprocessor and cache unit.

Claim 4

The system of claim 2 wherein said non-compliant device includes: (a) a plurality of scan registers for passing test data through each one of a plurality of logic elements; (b) means to select and read out said data from each one of said scan registers.

Claim 5

The system of claim 3 wherein said means to control includes: (i) means to generate a specialized Test Mode Select Signal to disable entry of the JTAG "pause" state in said non-compliant device.

Claim 6

The system of claim 4 wherein said means to control includes: (ii) means to generate a specialized Test Clock Signal to limit the specialized TAP controller to one clock period when it enters the Run-Test/Idle state.

Claim 7

On an integrated circuit having some logic elements capable and some logic elements not capable of test operations compatible with JTAG protocol, a system for boundary scan testing said integrated circuit without altering said JTAG protocol and without altering said non-compatible logic elements, said system comprising: (a) standard JTAG controller means for transmitting test data input signals to said devices compatible with JTAG protocol; (b) a specialized Test Access Port initiated by said standard JTAG Controller, for developing specialized control signal states to said non-compatible logic elements including: (b1) means to pass test data through said non-compatible logic elements for later transmission through compatible logic elements without compromising said JTAG protocol.

Claim 8

On an integrated circuit having some logic elements capable and some logic elements not capable of test operations compatible with JTAG protocol, a system for boundary scan testing said integrated circuit without altering said JTAG protocol and without altering said non-compatible logic elements, said system comprising: (a) standard JTAG controller means for transmitting test data input signals to said devices compatible with JTAG protocol; (b) a specialized Test Access Port initiated by said standard JTAG Controller, for developing specialized control signal states to said non-compatible logic elements including: (b1) means to pass test data through said non-compatible logic elements for later transmission through compatible logic elements without compromising said JTAG protocol.

Claim 9

In a network of digital modules having JTAG protocol compliant devices and non-compliant JTAG protocol devices, all subject to testing using the JTAG protocol, a system for enabling JTAG testing of both compliant and non-compliant devices without alteration of the non-compliant devices nor alteration of the JTAG protocol, said system comprising: (a) maintenance subsystem means for initiating testing of multiple devices connected to a standard JTAG controller said multiple devices including non-compliant JTAG protocol devices; (b) said standard JTAG controller generating a Test Clock (TCLK) signal and Test Mode Select (TMS) signal to each one of said compliant devices and to a specialized (STAP Test Access Port controller, said JTAG controller including: (b1) means to transmit a series of test data bits for passage through each one of said multiple devices. (b2) means to receive back said series of test data bits after passage through each of said multiple devices; (c) said specialized Test Access Port Controller (STAP) connected to each one of said non-compliant JTAG devices, each said specialized TAP controller connected to receive said Test Clock (TCLK) and Test Mode Select (TMS) signals from said standard JTAG Controller and including: (c1) means to generate a specialized Test Mode Select (RTMS) signal to said non-compliant JTAG device to disable entry of the JTAG "Pause" state in said non-compliant device; (c2) means to generate a specialized Test Clock (TCLK) signal to limit the specialized TAP controller to one clock period when it enters the Run Test/Idle state and to stop the entry of the Pause state.

Claim 10

In a network of digital modules having JTAG protocol compliant devices and non-compliant JTAG protocol devices, all subject to testing using the JTAG protocol, a system for enabling JTAG testing of both compliant and non-compliant devices without alteration of the non-compliant devices nor alteration of the JTAG protocol, said system comprising: (a) maintenance subsystem means for initiating testing of multiple devices connected to a standard JTAG controller said multiple devices including non-compliant JTAG protocol devices; (b) said standard JTAG controller generating a Test Clock (TCLK) signal and Test Mode Select (TMS) signal to each one of said compliant devices and to a specialized (STAP Test Access Port controller, said JTAG controller including: (b1) means to transmit a series of test data bits for passage through each one of said multiple devices. (b2) means to receive back said series of test data bits after passage through each of said multiple devices; (c) said specialized Test Access Port Controller (STAP) connected to each one of said non-compliant JTAG devices, each said specialized TAP controller connected to receive said Test Clock (TCLK) and Test Mode Select (TMS) signals from said standard JTAG Controller and including: (c1) means to generate a specialized Test Mode Select (RTMS) signal to said non-compliant JTAG device to disable entry of the JTAG "Pause" state in said non-compliant device; (c2) means to generate a specialized Test Clock (TCLK) signal to limit the specialized TAP controller to one clock period when it enters the Run Test/Idle state and to stop the entry of the Pause state.