Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
82 words
A semiconductor device utilizing a silicide reaction in which are provided a plurality of cells each having a semiconductor layer between a pair of conductors at least one of said pair of conductors is made of metal, the semiconductor layer between said at least pair of conductors made of amorphous silicon which silicide reacts with the metal of said conductors at a reaction speed of 10 m/sec or more to form a silicide region having a width of less than 150 nm.
Claim 2
Dependent Claim
82 words
A semiconductor device utilizing a silicide reaction in which are provided a plurality of cells each having a semiconductor layer between a pair of conductors at least one of said pair of conductors is made of metal, the semiconductor layer between said at least pair of conductors made of amorphous silicon which silicide reacts with the metal of said conductors at a reaction speed of 10 m/sec or more to form a silicide region having a width of less than 150 nm.
Claim 3
Dependent Claim
75 words
A semiconductor device utilizing a silicide reaction in which are provided a plurality of cells each having a semiconductor layer disposed between a pair of conductors, the semiconductor layers made of amorphous silicon, at least one said pair of conductors made of a metal which silicide reacts with said amorphous silicon to form a silicide region with one of a truncated conical-shaped and pyramid shaped structure and having a width of less than 150 nm.
Claim 4
Dependent Claim
75 words
A semiconductor device utilizing a silicide reaction in which are provided a plurality of cells each having a semiconductor layer disposed between a pair of conductors, the semiconductor layers made of amorphous silicon, at least one said pair of conductors made of a metal which silicide reacts with said amorphous silicon to form a silicide region with one of a truncated conical-shaped and pyramid shaped structure and having a width of less than 150 nm.
Claim 5
Dependent Claim
97 words
A semiconductor device utilizing a silicide reaction in which a plurality of cells are provided which each have a semiconductor layer between a pair of conductors, the semiconductor layer is made of amorphous silicon, at least one of the pair of conductors is made of metal which silicide reacts with the amorphous silicon to form a silicide region having a width of less than 150 nm, and the surface of the semiconductor or the metal is not exposed to an oxygen-containing atmosphere between a process for forming the amorphous silicon and a process for forming the metal.
Claim 6
Dependent Claim
97 words
A semiconductor device utilizing a silicide reaction in which a plurality of cells are provided which each have a semiconductor layer between a pair of conductors, the semiconductor layer is made of amorphous silicon, at least one of the pair of conductors is made of metal which silicide reacts with the amorphous silicon to form a silicide region having a width of less than 150 nm, and the surface of the semiconductor or the metal is not exposed to an oxygen-containing atmosphere between a process for forming the amorphous silicon and a process for forming the metal.
Claim 7
Dependent Claim
24 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein a thickness of the amorphous silicon is from 50 to 150 nm.
Claim 8
Dependent Claim
20 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the amorphous silicon layer is injected with ions.
Claim 9
Dependent Claim
25 words
A semiconductor device utilizing a silicide reaction according to claim 5, wherein the amorphous silicon layer is a layer injected with ions via the metal.
Claim 10
Dependent Claim
34 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein a surface of the semiconductor device is covered by an insulating film formed at a film forming temperature of 250° or less.
Claim 11
Dependent Claim
47 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein by supplying a current to the amorphous silicon layer through the pair of conductors, a silicide reaction is generated between the metal and the amorphous silicon and between the pair of conductors is electrically short-circuited.
Claim 12
Dependent Claim
23 words
A semiconductor device utilizing a silicide reaction according to claim 8, wherein the current flows from the amorphous silicon layer into the metal.
Claim 13
Dependent Claim
21 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the pair of conductors are both made of metal.
Claim 14
Dependent Claim
32 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the metal is a compound of a high melting point metal or an alloy including a high melting point metal.
Claim 15
Dependent Claim
30 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the metal includes at least one of Ta, Ti, Co, Hf, Ni, Zr, Cr, V, Pd and Pt.
Claim 16
Dependent Claim
17 words
A semiconductor device utilizing a silicide reaction according to claim 1, characterized by being formed by self-alignment.
Claim 17
Dependent Claim
32 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the semiconductor device is formed by self-alignment by means of a technique of selecting and growing a metal or semiconductor.
Claim 18
Dependent Claim
33 words
A semiconductor device utilizing a silicide reaction according to claim 14, wherein the semiconductor device is formed by self-alignment by means of a technique of selecting and growing W or Ti and silicon.
Claim 19
Dependent Claim
27 words
A semiconductor device utilizing a silicide reaction according to claim 1, further provided with means for electrically detecting a change in resistance between the pair of conductors.
Claim 20
Dependent Claim
40 words
A semiconductor device utilizing a silicide reaction according to claim 1, further provided with means for detecting a change in resistance between the pair of conductors by means of the silicide reaction and means for finishing the reaction after detection.
Claim 21
Dependent Claim
44 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein by inputting a pulse to one of the pair of conductors via a capacitor and instantaneously increasing a potential difference between the pair of conductors, breakdown of the amorphous silicon is generated.
Claim 22
Dependent Claim
43 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the cells are provided with a second semiconductor layer having a flow-rectifying characteristic between the semiconductor layer and the conductors or on a side opposite the semiconductor layer of the conductors.
Claim 23
Dependent Claim
22 words
A semiconductor device utilizing a silicide reaction according to claim 19, wherein a structure indicating the flow-rectifying characteristic is a PN connection.
Claim 24
Dependent Claim
22 words
A semiconductor device utilizing a silicide reaction according to claim 19, wherein a structure indicating the flow-rectifying characteristic is a Schottky connection.
Claim 25
Dependent Claim
29 words
A semiconductor device utilizing a silicide reaction according to claim 19, wherein the second semiconductor area has a structure with a resistance smaller than that of the semiconductor layer.
Claim 26
Dependent Claim
47 words
A semiconductor device utilizing a silicide reaction according to claim 22, wherein the semiconductor layer is made of nondoped amorphous silicon or amorphous silicon in which boron is doped to a specified amount and the second semiconductor layer is made of silicon in which impurities are doped.
Claim 27
Dependent Claim
37 words
A semiconductor device utilizing a silicide reaction according to claim 19, wherein the second semiconductor area has a structure made of a semiconductor material whose silicide reaction speed is slower than that of the first semiconductor area.
Claim 28
Dependent Claim
47 words
A semiconductor device utilizing a silicide reaction according to claim 24, wherein the semiconductor layer is amorphous silicon formed by means of ion injection and the second semiconductor layer is an amorphous silicon deposition film deposited by means of a vapor deposition method or a crystalline silicon.
Claim 29
Dependent Claim
49 words
A semiconductor device utilizing a silicide reaction according to claim 19, wherein a part of one of the pair of conductors adjacent to and in contact with the second semiconductor is formed of a metal which does not form a silicide layer by reacting with the second semiconductor area.
Claim 30
Dependent Claim
54 words
A semiconductor device utilizing a silicide reaction according to any of claim 1, wherein a plurality of first electrically conductive wirings and a plurality of second electrically conductive wirings are disposed in a matrix form and the cells are provided on an intersecting portion between the pluralities of first and second electrically conductive wirings.
Claim 31
Dependent Claim
45 words
A semiconductor device utilizing a silicide reaction according to claim 27, wherein the first electrically conductive wirings and the conductors adjacent thereto are formed of the same material and/or the second electrically conductive wirings and the conductors adjacent thereto are formed of the same material.
Claim 32
Dependent Claim
33 words
A semiconductor device utilizing a silicide reaction according to claim 27, wherein the electrical detecting means is provided with means for disabling detection of a change in resistance between the pair of conductors.
Claim 33
Dependent Claim
19 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the semiconductor device is a read-only memory.
Claim 34
Dependent Claim
25 words
A semiconductor device utilizing a silicide reaction according to claim 30, wherein the read-only memory is capable of storing data of 1 gigabit or higher.
Claim 35
Dependent Claim
28 words
A semiconductor device utilizing a silicide reaction according to claim 30, wherein the read-only memory is one from which data can be read in 20 nsec or less.
Claim 36
Dependent Claim
57 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein electrical connection and insulation between optional wirings can be arbitrarily determined by means of the silicide reaction after a manufacturing process is finished and thus a circuit function of a programmable logic array (PLA) or a field programmable gate array (FPGA) can be arbitrarily set.
Claim 37
Dependent Claim
48 words
A semiconductor device utilizing a silicide reaction according to any one of claim 1, wherein connection and insulation between a gate electrode of a MOS transistor and a power source or a grounding electrode can be arbitrarily determined by means of the silicide reaction after manufacturing is finished.
Claim 38
Dependent Claim
45 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein connection and insulation between a source electrode and/or a drain electrode of the MOS transistor and a grounding electrode can be arbitrarily determined by means of the silicide reaction after manufacturing is finished.
Claim 39
Dependent Claim
117 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein in a neuron MOS transistor having a semiconductor area of one conductivity type on a base plate, source and drain areas of opposite conductivity types provided in this area, a floating gate electrode provided in an area in which the source and drain areas are separated via the insulating film and in an electrically floating state and a plurality of input gate electrodes capacitive-coupled via the floating gate electrodes and the insulating film, connection and insulation between the plurality of input gate electrodes and the power source or the grounding electrode can be arbitrarily determined by means of the silicide reaction after manufacturing is finished.
Claim 40
Dependent Claim
31 words
A semiconductor device utilizing a silicide reaction according to claim 1, wherein the silicide reaction is generated while cooling a base plate temperature by means of a liquid or a gas.