Memory system ensuring coherency for memory buffers in a data communication system

Claim 2

A memory system for storing data messages communicated between a processor unit and a communication module, the memory system comprising: a memory array having a plurality of memory buffers, each buffer for storing a data message comprising at least two data words; first logic circuitry for generating a lock signal for a memory buffer of the plurality of memory buffers, the lock signal being valid when the processor unit reads the first data word of the data message stored in the memory buffer whilst the memory buffer is not being accessed by the communication module, the lock signal for the memory buffer being invalidated when the processor unit reads the first data word of the data message stored in a different memory buffer; module decode logic coupled to the first logic circuitry for receiving the lock signal, the module decode logic preventing the communication module from writing a data message to the memory buffer when a valid lock signal has been generated by the first logic circuitry for that memory buffer and allowing the data message to be written to the memory buffer when the lock signal for that memory buffer is invalidated; and second logic circuitry for generating and providing a busy signal to the processor unit when the processor unit reads the first data word from the memory buffer, the busy signal forming part of the first data word read from the memory buffer, and having a first logic state when the memory buffer is being written to by the communication module and having a second logic state when the memory buffer is not being written to by the communication module.

Claim 3

A memory system according to claim 1 wherein the first logic circuitry comprises: a register having an input for receiving an address of the memory buffer generated by the processor unit and for storing an address value representing the received address, the register further having an output coupled to the module decode logic; logic gate circuitry having a first input coupled to receive a first word read signal generated when the processor unit reads the first data word from the memory buffer, a second input coupled to receive the busy signal and an output for providing an output signal; latch circuitry having an input coupled to the output of the logic gate circuitry and an output for providing the lock signal to the module decode logic, the latch circuitry providing the valid lock signal or the invalidated lock signal in dependence on the logic state of the output signal at the output of the logic gate circuitry.

Claim 4

A memory system according to claim 2 wherein the module decode logic comprises: comparator circuitry having a first input coupled to the output of the register to receive the address value stored in the register, a second input coupled to receive the address of a memory buffer generated by the communication module and an output for providing a match signal when the address value at the first input corresponds to the address at the second input and a no-match signal when the address value at the first input does not match the address at the second input; and logic coupled to the output of the comparator circuitry and to receive the lock signal for generating a signal which prevents the communication module from writing a data message to the memory buffer when the match signal is provided at the output of the comparator circuitry and the lock signal is valid or a signal which allows the communication module to write a data message to the memory buffer when the no-match signal is provided at the output of thee comparator circuitry or when the lock signal is invalidated.

Claim 5

A memory system according to claim 3 wherein the logic gate circuitry comprises: an AND gate having a first input coupled to the first input of the logic gate circuitry, a second input and an output coupled to the output of the logic gate circuitry; and a NOT gate having an input coupled to receive the busy signal and an output coupled to the second input of the AND gate.

Claim 6

A memory system according to claim 2 wherein the latch circuitry has a second input coupled to receive a control signal from the processor unit, the latch circuitry invalidating the lock signal in response to receiving the control signal.

Claim 7

A memory system according to claim 1 wherein the first logic circuitry generates a lock signal comprising a lock signal valid bit, the lock signal being valid when the lock signal valid bit has a first logic state and being invalidated when the lock signal valid bit has a second logic state.

Claim 8

A memory system according to claim 1 wherein the lock signal is invalidated in response to a control signal generated by the processor unit.

Claim 9

A memory system according to claim 1 wherein the second logic circuitry comprises: circuitry comprising: comparator circuitry having a first input coupled to receive the address of the memory buffer which is generated by the processor unit and a second input coupled to receive the address of a memory buffer which is generated by the communication module and an output for providing a match signal when the address at the first input corresponds to the address at the second input and a no-match signal when the address at the first input does not correspond to the address at the second input, and logic coupled to the output of the comparator circuitry and to receive a communication module write signal, the logic providing the busy signal having the first logic state when the match signal is provided at the output of the comparator circuitry and the communication module write signal indicates the communication module is writing to the memory buffer or the busy signal having the second logic state when the no-match signal is provided at the output of the comparator circuitry or when the communication module write signal indicates the communication module is not writing to the memory buffer; and a multiplexer having a first input coupled to receive a bit of each data word of the data message when a data message is read by the processor unit, a second input coupled to receive the busy signal and a control input coupled to receive a first word read signal generated by the processor unit, the first word read signal having a first logic state when the processor unit reads the first data word from the memory buffer and a second logic state when the processor unit is not reading the first data word from the memory buffer, and an output for transferring the bit or the busy signal to the processor unit as part of the data word read from the memory buffer depending on which input of the first and second inputs is selected, the multiplexer selecting the second input in response to receiving the first word read signal having the first logic state and selecting the first input in response to receiving the first word read signal having the second logic state.

Claim 10

A memory system according to claim 1 wherein the busy signal forms a bit of the first data word of the data message as the processor unit reads the data message from the memory buffer.

Claim 11

A memory system according to claim 9 wherein the busy signal forms the Least Significant Bit (LSB) of the first data word of the data message as the processor unit reads the data message from the memory buffer.

Claim 12

A data communications system comprising: a processor unit for transmitting and receiving data messages; a communication module for transmitting and receiving data messages; and a memory system for storing data messages received from the communication module for subsequent transmission to the processor unit and for storing data messages received from the processor unit for subsequent transmission to the communication module, the memory system comprising: a memory array having a plurality of memory buffers, each buffer for storing a data message comprising at least two data words; first logic circuitry for generating a lock signal for a memory buffer of the plurality of memory buffers, the lock signal being valid when the processor unit reads the first data word of the data message stored in the memory buffer whilst the memory buffer is not being accessed by the communication module, the lock signal for the memory buffer being invalidated when the processor unit reads the first data word of the data message stored in a different memory buffer; module decode logic coupled to the first logic circuitry for receiving the lock signal, the module decode logic preventing the communication module from writing a data message to the memory buffer when a valid lock signal has been generated by the first logic circuitry for that memory buffer and allowing the data message to be written to the memory buffer when the lock signal for that memory buffer is invalidated; and second logic circuitry for generating and providing a busy signal to the processor unit when the processor unit reads the first data word from the memory buffer, the busy signal forming part of the first data word read from the memory buffer, and having a first logic state when the memory buffer is being written to by the communication module and having a second logic state when the memory buffer is not being written to by the communication module.

Claim 13

A data communications system comprising: a processor unit for transmitting and receiving data messages; a communication module for transmitting and receiving data messages; and a memory system for storing data messages received from the communication module for subsequent transmission to the processor unit and for storing data messages received from the processor unit for subsequent transmission to the communication module, the memory system comprising: a memory array having a plurality of memory buffers, each buffer for storing a data message comprising at least two data words; first logic circuitry for generating a lock signal for a memory buffer of the plurality of memory buffers, the lock signal being valid when the processor unit reads the first data word of the data message stored in the memory buffer whilst the memory buffer is not being accessed by the communication module, the lock signal for the memory buffer being invalidated when the processor unit reads the first data word of the data message stored in a different memory buffer; module decode logic coupled to the first logic circuitry for receiving the lock signal, the module decode logic preventing the communication module from writing a data message to the memory buffer when a valid lock signal has been generated by the first logic circuitry for that memory buffer and allowing the data message to be written to the memory buffer when the lock signal for that memory buffer is invalidated; and second logic circuitry for generating and providing a busy signal to the processor unit when the processor unit reads the first data word from the memory buffer, the busy signal forming part of the first data word read from the memory buffer, and having a first logic state when the memory buffer is being written to by the communication module and having a second logic state when the memory buffer is not being written to by the communication module.

Claim 14

A memory system according to claim 11 wherein the first logic circuitry comprises: a register having an input for receiving an address of the memory buffer generated by the processor unit and for storing an address value representing the received address, the register further having an output coupled to the module decode logic; logic gate circuitry having a first input coupled to receive a first word read signal generated when the processor unit reads the first data word from the memory buffer, a second input coupled to receive the busy signal and an output for providing an output signal; latch circuitry having an input coupled to the output of the logic gate circuitry and an output for providing the lock signal to the module decode logic, the latch circuitry providing the valid lock signal or the invalidated lock signal in dependence on the logic state of the output signal at the output of the logic gate circuitry.

Claim 15

A memory system according to claim 12 wherein the module decode logic comprises: comparator circuitry having a first input coupled to the output of the register to receive the address value stored in the register, a second input coupled to receive the address of a memory buffer generated by the communication module and an output for providing a match signal when the address value at the first input corresponds to the address at the second input and a no-match signal when the address value at the first input does not match the address at the second input; and logic coupled to the output of the comparator circuitry and to receive the lock signal for generating a signal which prevents the communication module from writing a data message to the memory buffer when the match signal is provided at the output of the comparator circuitry and the lock signal is valid or a signal which allows the communication module to write a data message to the memory buffer when the no-match signal is provided at the output of the comparator circuitry or when the lock signal is invalidated.

Claim 16

A memory system according to claim 13 wherein the logic gate circuitry comprises: an AND gate having a first input coupled to the first input of the logic gate circuitry, a second input and an output coupled to the output of the logic gate circuitry; and a NOT gate having an input coupled to receive the busy signal and an output coupled to the second input of the AND gate.

Claim 17

A memory system according to claim 12 wherein the latch circuitry has a second input coupled to receive a control signal from the processor unit, the latch circuitry invalidating the lock signal in response to receiving the control signal.

Claim 18

A memory system according to claim 11 wherein the first logic circuitry generates a lock signal comprising a lock signal valid bit, the lock signal being valid when the lock signal valid bit has a first logic state and being invalidated when the lock signal valid bit has a second logic state.

Claim 19

A memory system according to claim 11 wherein the lock signal is invalidated in response to a control signal generated by the processor unit.

Claim 20

A memory system according to claim 11 wherein the second logic circuitry comprises: circuitry comprising: comparator circuitry having a first input coupled to receive the address of the memory buffer which is generated by the processor unit and a second input coupled to receive the address of a memory buffer which is generated by the communication module and an output for providing a match signal when the address at the first input corresponds to the address at the second input and a no-match signal when the address at the first input does not correspond to the address at the second input; and logic coupled to the output of the comparator circuitry and to receive a communication module write signal, the logic providing the busy signal having the first logic state when the match signal is provided at the output of the comparator circuitry and the communication module write signal indicates the communication module is writing to the memory buffer or the busy signal having the second logic state when the no-match signal is provided at the output of the comparator circuitry or when the communication module write signal indicates the communication module is not writing to the memory buffer; and a multiplexer having a first input coupled to receive a bit of each data word of the data message when a data message is read by the processor unit, a second input coupled to receive the busy signal and a control input coupled to receive a first word read signal generated by the processor unit, the first word read signal having a first logic state when the processor unit reads the first data word from the memory buffer and a second logic state when the processor unit is not reading the first data word from the memory buffer, and an output for transferring the bit or the busy signal to the processor unit as part of the data word read from the memory buffer depending on which input of the first and second inputs is selected, the multiplexer selecting the second input in response to receiving the first word read signal having the first logic state and selecting the first input in response to receiving the first word read signal having the second logic state.

Claim 21

A memory system according to claim 11 wherein the busy signal forms a bit of the first data word of the data message as the processor unit reads the data message from the memory buffer.

Claim 22

A memory system according to claim 19 wherein the busy signal forms the Least Significant Bit (LSB) of the first data word of the data message as the processor unit reads the data message from the memory buffer.