Patent US5737583A successfully refreshed from Google Patents.
US5737583A
Expired / Lapsed
US
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Digital circuit simulation
Assignee: ARM Ltd
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Filing: 1995-09-12
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Granted: 1998-04-07
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Expires: 2015-09-12
Abstract
Abstract A primary circuit model using a primary simulator 40' operates in conjunction with a plurality of secondary circuit models 10, 20, 30 using a secondary simulator 100. Only signals external to the secondary circuit models are passed between the primary simulator and the secondary simulator. The primary simulator and the secondary simulator independently increment their simulated time when they are active. The secondary simulator is invoked when a signal to which one of the secondary circuit models is responsive is changed by the primary simulator. The secondary simulator is not exited until no further signal changes are being driven by the secondary circuit models at which stage the last asserted values of signals changed by the secondary circuit models are returned to the primary model. If there are pending signal changes within the secondary simulation when it is entered in response to a signal from the primary simulator, then that primary simulator signal is buffered until those pending signal changes have taken place.
Inventors
- 👤 Clive Richard Jones
- 👤 Richard William Earnshaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:03
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
269 words
A method of simulating a digital circuit comprising a primary circuit coupled to a plurality of secondary circuits using a primary circuit model and a plurality of secondary circuit models, the primary circuit model being a logic model and each of the plurality of secondary circuit models being logic models, said method comprising the steps of: (i) simulating with said primary circuit model signals exchanged within said primary circuit, said primary circuit model operating through a sequence of primary simulated times separated by primary time increments: (ii) when said primary circuit model advances to a primary simulated time at which said primary circuit model changes a signal value to which at least one of said secondary circuit models is responsive, stopping simulating signals exchanged within said primary circuit, stopping incrementing said primary simulated time and passing said signal to said at least one of said secondary circuit models; (iii) simulating with said plurality of secondary circuit models signals exchanged between said plurality of secondary circuits, said plurality of secondary circuit models operating through a sequence of secondary simulated times separated by secondary time increments; (iv) detecting when no further signal exchanges are driven by said plurality of secondary circuit models and thereupon stopping incrementing said secondary simulated time and passing to said primary circuit model the last asserted value of any signals changed by said plurality of secondary circuit models during incrementing of said secondary simulated time and to which said primary circuit model is responsive; and (v) restarting simulation with said primary circuit model of signals exchanged within said primary circuit and incrementing of said primary simulated time.
Claim 2
Independent Claim
269 words
A method of simulating a digital circuit comprising a primary circuit coupled to a plurality of secondary circuits using a primary circuit model and a plurality of secondary circuit models, the primary circuit model being a logic model and each of the plurality of secondary circuit models being logic models, said method comprising the steps of: (i) simulating with said primary circuit model signals exchanged within said primary circuit, said primary circuit model operating through a sequence of primary simulated times separated by primary time increments: (ii) when said primary circuit model advances to a primary simulated time at which said primary circuit model changes a signal value to which at least one of said secondary circuit models is responsive, stopping simulating signals exchanged within said primary circuit, stopping incrementing said primary simulated time and passing said signal to said at least one of said secondary circuit models; (iii) simulating with said plurality of secondary circuit models signals exchanged between said plurality of secondary circuits, said plurality of secondary circuit models operating through a sequence of secondary simulated times separated by secondary time increments; (iv) detecting when no further signal exchanges are driven by said plurality of secondary circuit models and thereupon stopping incrementing said secondary simulated time and passing to said primary circuit model the last asserted value of any signals changed by said plurality of secondary circuit models during incrementing of said secondary simulated time and to which said primary circuit model is responsive; and (v) restarting simulation with said primary circuit model of signals exchanged within said primary circuit and incrementing of said primary simulated time.
Claim 3
Dependent Claim
29 words
A method as claimed in claim 1, wherein said plurality of secondary circuit models exchange only signals external to said plurality of secondary circuits with said primary circuit models.
Claim 4
Dependent Claim
30 words
A method as claimed in claim 1, wherein said plurality of secondary circuit models exchange with one another signals external to and internal to said plurality of secondary circuit models.
Claim 5
Dependent Claim
48 words
A method as claimed in claim 1, wherein any of said plurality of secondary circuit models may issue a priority signal to said primary circuit model that is passed to said primary circuit model whilst signal exchanges are still being driven by said plurality of secondary circuit models.
Claim 6
Dependent Claim
82 words
A method as claimed in claim 4, wherein, if said priority signal triggers passing of one or more further signals from said primary circuit model to said plurality of secondary circuit models, then said one or more further signals are buffered and not applied to said plurality of secondary circuit models until no further signal exchanges are driven by said plurality of secondary circuit models resulting from the state of said plurality of secondary circuit models preceding issue of said priority signal.
Claim 7
Dependent Claim
25 words
A method as claimed in claim 1, wherein at least some of said primary simulated time increments are delta time increments of substantially zero length.
Claim 8
Dependent Claim
25 words
A method as claimed in claim 1, wherein at least some of said secondary simulated time increments are delta time increments of substantially zero length.
Claim 9
Dependent Claim
40 words
A method as claimed in claim 1, wherein said primary circuit model passes a signal to an interface controller that buffers and redirects said signal to those of said plurality of secondary circuit models that are responsive to said signal.
Claim 10
Dependent Claim
38 words
A method as claimed in claim 8, wherein said interface controller stores data indicative of the asserted value of signals changed by said plurality of secondary circuit models and the secondary simulated time at which those changes occurred.
Claim 11
Dependent Claim
32 words
A method as claimed in claim 1, wherein said primary circuit model comprises a general purpose data processing apparatus operating under the control of primary program instructions to model said primary circuit.
Claim 12
Dependent Claim
35 words
A method as claimed in claim 10, wherein said plurality of secondary circuit models comprise said general purpose data processing apparatus operating under control of secondary program instructions to model said plurality of secondary circuits.
Claim 13
Dependent Claim
35 words
A method as claimed in claim 11, wherein said plurality of secondary circuit models represent a microprocessor circuit and said primary circuit model represents one or more devices to be connected to said microprocessor circuit.
Claim 14
Independent Claim
272 words
An apparatus for simulating a digital circuit comprising a primary circuit coupled to a plurality of secondary circuits, said apparatus comprising: (i) a primary circuit model for simulating signals exchanged within said primary circuit, said primary circuit model operating through a sequence of primary simulated times separated by primary time increments; (ii) a plurality of secondary circuit models for simulating signals exchanged between said plurality of secondary circuits, said plurality of secondary circuit models operating through a sequence of secondary simulated times separated by secondary time increments; and (iii) an interface controller for controlling the passing of signals between said primary circuit model and said plurality of secondary circuit models; wherein, (iv) when said primary circuit model advances to a primary simulated time at which said primary circuit model changes a signal value to which at least one of said secondary circuit models is responsive, said primary circuit model stops simulating signals exchanged within said primary circuit, stops incrementing said primary simulated time and passes said signal via said interface controller to said at least one of said secondary circuit models; and (v) a detector for detecting when no further signal exchanges are driven by said plurality of secondary circuit models, said interface controller then stopping the incrementing of said secondary simulated time and passing to said primary circuit model the last asserted value of any signals changed by said plurality of secondary circuit models during incrementing of said secondary simulated time and to which said primary circuit model is responsive, whereupon said primary circuit model restarts simulation of signals exchanged within said primary circuit and incrementing of said primary simulated time.
Claim 15
Independent Claim
272 words
An apparatus for simulating a digital circuit comprising a primary circuit coupled to a plurality of secondary circuits, said apparatus comprising: (i) a primary circuit model for simulating signals exchanged within said primary circuit, said primary circuit model operating through a sequence of primary simulated times separated by primary time increments; (ii) a plurality of secondary circuit models for simulating signals exchanged between said plurality of secondary circuits, said plurality of secondary circuit models operating through a sequence of secondary simulated times separated by secondary time increments; and (iii) an interface controller for controlling the passing of signals between said primary circuit model and said plurality of secondary circuit models; wherein, (iv) when said primary circuit model advances to a primary simulated time at which said primary circuit model changes a signal value to which at least one of said secondary circuit models is responsive, said primary circuit model stops simulating signals exchanged within said primary circuit, stops incrementing said primary simulated time and passes said signal via said interface controller to said at least one of said secondary circuit models; and (v) a detector for detecting when no further signal exchanges are driven by said plurality of secondary circuit models, said interface controller then stopping the incrementing of said secondary simulated time and passing to said primary circuit model the last asserted value of any signals changed by said plurality of secondary circuit models during incrementing of said secondary simulated time and to which said primary circuit model is responsive, whereupon said primary circuit model restarts simulation of signals exchanged within said primary circuit and incrementing of said primary simulated time.
References Cited (Backward Citations)
US4342093A
Cited
GB2229300A
Cited
US5081601A
Cited
US5613062A
Cited
GB2248321A
Cited
US5193068A
Cited
US5410673A
Cited
US5426768A
Cited
US5475832A
Cited
US5603015A
Cited
US5493672A
Cited
US5546562A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |