Patent US5752006A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5752006A Expired / Lapsed US ⏱️ 0.0 years remaining

Configuration emulation of a programmable logic device

Assignee: Xilinx Inc
•
Filing: 1996-02-29
•
Granted: 1998-05-12
•
Expires: 2016-02-29
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A configuration emulation circuit generates configuration signals to emulate a programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Inventors

  • 👤 Glenn A. Baxter

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 15:53
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 125 words
A circuit for emulating a configuration timing relationship and a configuration protocol relationship between a programmable Logic Device (PLD) and a programming circuit, said programming circuit using a configuration mode signal to said PLD to establish said configuration timing relationship and said configuration protocol relationship, said circuit comprising: a first circuit to emulate said PLD in said configuration timing relationship; and a second circuit to emulate said PLD in said configuration protocol relationship, said second circuit being coupled to said first circuit and being coupled to receive said configuration mode signal, and wherein said second circuit is responsive to said configuration mode signal, said second circuit further configured to emulate said PLD in a second configuration protocol relationship responsive to a second configuration mode signal.
Claim 2
Dependent Claim 125 words
A circuit for emulating a configuration timing relationship and a configuration protocol relationship between a programmable Logic Device (PLD) and a programming circuit, said programming circuit using a configuration mode signal to said PLD to establish said configuration timing relationship and said configuration protocol relationship, said circuit comprising: a first circuit to emulate said PLD in said configuration timing relationship; and a second circuit to emulate said PLD in said configuration protocol relationship, said second circuit being coupled to said first circuit and being coupled to receive said configuration mode signal, and wherein said second circuit is responsive to said configuration mode signal, said second circuit further configured to emulate said PLD in a second configuration protocol relationship responsive to a second configuration mode signal.
Claim 3
Dependent Claim 47 words
The circuit of claim 1 wherein said first circuit includes a power stable circuit and a power on reset circuit, said power stable circuit indicating a stable power supply to said circuit, said power on reset circuit to reset said circuit responsive to said power stable circuit.
Claim 4
Dependent Claim 49 words
The circuit of claim 1 wherein said second circuit includes a PLD family type and a PLD device type specified configuration protocol emulation circuit, said PLD family type and said PLD device type defining a set of configuration modes to be emulated and a set of configuration programming characteristics.
Claim 5
Dependent Claim 26 words
The circuit of claim 3 wherein said set of configuration programming characteristics includes a number of bits per frame characteristic and a number of frames characteristic.
Claim 6
Dependent Claim 19 words
The circuit of claim 3 wherein said family type is included in and is defined by said device type.

References Cited (Backward Citations)

US4901259A Cited
US5552722A Cited
WO1994020909A1 Cited
US5550839A Cited
US5596742A Cited
US5652904A Cited
US5526278A Cited
US5604888A Cited
US5546562A Cited
US5649176A Cited
US5594367A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-05-11 2001-11-10 2002-05-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-05-11 2005-11-10 2006-05-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-05-11 2009-11-10 2010-05-12 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag