Computer architecture incorporating processor clusters and hierarchical cache memories

Claim 2

A cache architecture for a computer system having multiple processors comprising: a plurality of level one caches, each said level one cache being operatively coupled to one of the multiple processors of the computer system to form a plurality of processor-level oNE cache pairs and each said level one cache being a store-through cache; a plurality of level two caches, each of said level two caches being operatively coupled to two or more of said processor-level one cache pairs to form a cluster, and each of said level two caches having a plurality of level two directory states for the purpose of maintaining coherency among all of said caches; wherein for each said level two cache said level two directory states describe the status of the data stored in said level two cache as being invalid, exclusive to said level two cache, or read only to said level two cache; and wherein for each said level two cache said level two directory states describe the status of the data stored in said level one caches that are operatively coupled to said level two cache as being invalid, exclusive to one of said level once caches that are operatively coupled to said level two cache, or read only to one or more of said level one caches that are operatively coupled to said level two cache; wherein when a level one cache within a cluster updates the data, the status of the level two directory states is examined and castouts sent only to the level one caches that have exclusive or read only ownership of the data; a plurality of point to point buses, each said point to point bus coupling one of said processor-level one cache pairs to one of said level two caches; a shared bus, said shared bus coupling together said level two caches; and wherein each of said level two caches further comprise a shared bus castout buffer for temporary storage of data in response to one of either a snoop command or a store command.

Claim 3

A cache architecture according to claim 1, wherein a parity check is performed on the level one caches.

Claim 4

A cache architecture according to claim 1, wherein each said processor-level one cache pair is housed within a single microchip.

Claim 5

A cache architecture according to claim 1, wherein each of said level two caches comprise a plurality of cache interleaves for storing data received over said point to point buses and over said shared bus, each of said interleaves being separately accessible so that any two or more interleaves can be accessed during a single machine cycle.

Claim 6

A cache architecture according to claim 4, wherein each of said level two caches further comprises a cache controller for coordinating accesses to said interleaves.

Claim 7

A cache architecture according to claim 1, wherein each of said level two caches comprise a directory for storing one or more directory states describing the state of the data residing in said level two cache.

Claim 8

A cache architecture according to claim 6, wherein each of said level two caches further comprise: one or more central processor controllers, each said central processor controller being used to manage requests from one of said plurality of level one caches; and a shared bus controller for managing communications between said level two cache and said shared bus.

Claim 9

A cache architecture according to claim 7, wherein each of said level two caches further comprises a pipeline processor for performing operations in response to requests from said central processor controllers and said shared bus controller.

Claim 10

A cache architecture according to claim 8, wherein each of said level two caches further comprises: a shared bus line buffer for receiving said shared bus.

Claim 11

A cache architecture according to claim 9, wherein each of said level two caches further comprises: a line fetch address register for processing fetch requests by the processors for data that is not stored within said level two cache; and a line store address register for determining which data to remove from said level two cache when it is necessary to make room for new data.

Claim 12

A cache architecture according to claim 9, wherein each of said level two caches further comprises one or more store stacks, each said store stack being used to hold data accompanying store requests from one of said plurality of level one caches.

Claim 13

An architecture for a computer system having multiple processors, comprising: a plurality of level one caches, each said level one cache being operatively coupled at one of the processors of the computer system to form a plurality of processor-level one cache pairs and each said level one cache being a store-through cache; a plurality of level two caches, each of said level two caches being operatively coupled to two or more of said processor-level one cache pairs to form a cluster, and each of said level two caches having a plurality of level two directory states for the purpose of maintaining coherency among all of said caches; wherein for each said level two cache said level two directory states describe the status of the data stored in said level two cache as being invalid, exclusive to said level two cache, or read only to said level two cache; and wherein for each said level two cache said level two directory states describe the status of the data stored in said level one caches that are operatively coupled to said level two cache as being invalid, exclusive to one of said level one caches that are operatively coupled to said level two cache, or read only to one or more of said level one caches that are operatively coupled to said level two cache; wherein when a level one cache within a cluster updates the data, the status of the level two directory states is examined and castouts sent only to the level one caches that have exclusive or read only ownership of the data; a plurality of point to point buses, each said point to point bus coupling one of said processor-level one cache pairs to one of said level two caches; a shared bus, said shared bus coupling together said level two caches, a system memory coupled to said shared bus, and wherein each of said level two caches further comprise a shared bus castout buffer for temporary storage of data in response to one of either a snoop command or a store command.

Claim 14

An architecture for a computer system having multiple processors, comprising: a plurality of level one caches, each said level one cache being operatively coupled at one of the processors of the computer system to form a plurality of processor-level one cache pairs and each said level one cache being a store-through cache; a plurality of level two caches, each of said level two caches being operatively coupled to two or more of said processor-level one cache pairs to form a cluster, and each of said level two caches having a plurality of level two directory states for the purpose of maintaining coherency among all of said caches; wherein for each said level two cache said level two directory states describe the status of the data stored in said level two cache as being invalid, exclusive to said level two cache, or read only to said level two cache; and wherein for each said level two cache said level two directory states describe the status of the data stored in said level one caches that are operatively coupled to said level two cache as being invalid, exclusive to one of said level one caches that are operatively coupled to said level two cache, or read only to one or more of said level one caches that are operatively coupled to said level two cache; wherein when a level one cache within a cluster updates the data, the status of the level two directory states is examined and castouts sent only to the level one caches that have exclusive or read only ownership of the data; a plurality of point to point buses, each said point to point bus coupling one of said processor-level one cache pairs to one of said level two caches; a shared bus, said shared bus coupling together said level two caches, a system memory coupled to said shared bus, and wherein each of said level two caches further comprise a shared bus castout buffer for temporary storage of data in response to one of either a snoop command or a store command.

Claim 15

An architecture according to claim 12, further comprising an input/output device for communicating with said processors, and for transmitting data to and from the processors and said system memory.

Claim 16

An architecture according to claim 12, wherein a parity check is performed on the level one caches.

Claim 17

An architecture according to claim 12, wherein each said processor-level one cache pair is housed within a single microchip.

Claim 18

An architecture according to claim 12, wherein each of said level two caches comprise a plurality of cache interleaves for storing data received over said point to point buses, each of said interleaves being separately accessible so that any two or more interleaves can be accessed during a single machine cycle.

Claim 19

An architecture according to claim 16, wherein each of said level two caches further comprises a cache controller for coordinating accesses to said interleaves.

Claim 20

A architecture according to claim 12, wherein each of said level two caches comprise a directory for storing one or more directory states describing the state of the data residing in said level two cache.

Claim 21

An architecture according to claim 18, wherein each of said level two caches further comprise: one or more central processor controllers, each said central processor controller being used to manage requests from one of said plurality of level one caches; and a shared bus controller for managing communications between said level two cache and said shared bus.

Claim 22

An architecture according to claim 19, wherein each of said level two caches further comprises a pipeline processor for performing operations in response to requests from said central processor controllers and said shared bus controller.

Claim 23

An architecture according to claim 20, wherein each of said level two caches further comprises: a shared bus line buffer for receiving data over said shared bus.

Claim 24

An architecture according to claim 21, wherein each of said level two caches further comprises: a line fetch address register for processing fetch requests by the processors for data that is not stored within said level two cache; and a line store address register for determining which data to remove from said level two cache when it is necessary to make room for new data.

Claim 25

An architecture according to claim 22, wherein each of said level two caches further comprises one or more store stacks, each said store stack being used to hold data accompanying store requests from one of said plurality of level one caches.

Claim 26

A hierarchical cable architecture for a computer system having multiple processors, comprising: a shared bus; a plurality of level two caches, each said level two cache coupled to said shared bus; a plurality level one caches, each said level one cache being operatively coupled to one of the processors to form a plurality of processor-level one cache pairs and each said level one cache being a store-through cache; wherein each of said level two caches have a plurality of level two directory states for the purpose of maintaining coherency among all of said caches; wherein for each said level two cache said level two directory states describe the status of the data stored in said level two cache as being invalid, exclusive to said level two cache, or read only to said level two cache; wherein for each said level two cache said level two directory states describe the status of the data stored in said level one caches that are operatively coupled to said level two cache as being invalid, exclusive to one of said level one caches that are operatively coupled to said level two cache, or read only to one or more of said level one caches that are operatively coupled to said level two cache; wherein when a level one cache within a cluster updates the data, the status of the level two directory states is examined and castouts sent only to the level one caches that have exclusive or read only ownership of the data; and wherein each of said level two caches further comprise a shared bus castout buffer for temporary storage of data in response to one of either a snoop command or a store command.

Claim 27

A hierarchical cable architecture for a computer system having multiple processors, comprising: a shared bus; a plurality of level two caches, each said level two cache coupled to said shared bus; a plurality level one caches, each said level one cache being operatively coupled to one of the processors to form a plurality of processor-level one cache pairs and each said level one cache being a store-through cache; wherein each of said level two caches have a plurality of level two directory states for the purpose of maintaining coherency among all of said caches; wherein for each said level two cache said level two directory states describe the status of the data stored in said level two cache as being invalid, exclusive to said level two cache, or read only to said level two cache; wherein for each said level two cache said level two directory states describe the status of the data stored in said level one caches that are operatively coupled to said level two cache as being invalid, exclusive to one of said level one caches that are operatively coupled to said level two cache, or read only to one or more of said level one caches that are operatively coupled to said level two cache; wherein when a level one cache within a cluster updates the data, the status of the level two directory states is examined and castouts sent only to the level one caches that have exclusive or read only ownership of the data; and wherein each of said level two caches further comprise a shared bus castout buffer for temporary storage of data in response to one of either a snoop command or a store command.

Claim 28

A hierarchical cache architecture according to claim 24, wherein a parity check is performed on the level one caches.

Claim 29

A hierarchical cache architecture according to claim 24, wherein each said processor-level one cache pair is housed within a single microchip.