Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; a second column selection circuit for selecting a second bit line from the plurality of second bit lines; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 3

A semiconductor memory device according to claim 1, further comprising a first charger for charging the selected first bit line so that the selected first bit line obtains a first potential.

Claim 4

A semiconductor memory device according to claim 1, further comprising a second charger for charging the selected second bit line so that the selected second bit line obtains a second potential.

Claim 5

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; a second column selection circuit for selecting a second bit line from the plurality of second bit lines; a first discharger for discharging the selected first bit line and a second discharger for discharging the selected second bit line; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to another one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 6

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; a second column selection circuit for selecting a second bit line from the plurality of second bit lines; a first discharger for discharging the selected first bit line and a second discharger for discharging the selected second bit line; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to another one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 7

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; second column selection circuit for selecting a second bit line from the plurality of second bit lines; a first discharger for discharging the selected first bit line; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 8

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; second column selection circuit for selecting a second bit line from the plurality of second bit lines; a first discharger for discharging the selected first bit line; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 9

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; first column selection circuit for selecting a first bit line from the plurality of first bit lines; second column selection circuit for selecting a second bit line from the plurality of second bit lines; a leakage circuit for allowing a current flowing through the selected second bit line to leak; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 10

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; first column selection circuit for selecting a first bit line from the plurality of first bit lines; second column selection circuit for selecting a second bit line from the plurality of second bit lines; a leakage circuit for allowing a current flowing through the selected second bit line to leak; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 11

A semiconductor memory device according to claim 4, further comprising a first charger for charging the selected first bit line so that the selected first bit line obtains a first potential, wherein the first and second dischargers discharge the selected first and second bit lines for a certain duration, and the first charger charges the selected first bit line after the certain duration has passed from a predetermined time so that the selected first bit line reaches the first potential.

Claim 12

A semiconductor memory device according to claim 1, wherein the respective second bit lines are provided on a ground level side of the memory cells.

Claim 13

A semiconductor memory device according to claim 1, wherein each of the second bit lines is coupled to a ground level.

Claim 14

A semiconductor memory device according to claim 6, further comprising a discharger for discharging the selected second bit line.

Claim 15

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; a second column selection circuit for selecting a second bit line from the plurality of second bit lines; a first charger for charging the selected first bit line and a second charger for charging the selected second bit line so that the selected first and second bit lines obtain a first potential and a second potential, respectively; a discharger for discharging the selected second bit line; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.

Claim 16

A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a first column selection circuit for selecting a first bit line from the plurality of first bit lines; a second column selection circuit for selecting a second bit line from the plurality of second bit lines; a first charger for charging the selected first bit line and a second charger for charging the selected second bit line so that the selected first and second bit lines obtain a first potential and a second potential, respectively; a discharger for discharging the selected second bit line; and an amplifier, wherein each of the plurality of memory cells includes a drain electrode, a source electrode, and a gate electrode, and the plurality of memory cells are classified into a plurality of column groups, where the drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line, the source electrodes of the memory cells belonging to the same column group are connected to the same second bit line, and the gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via one of the plurality of word lines, and the amplifier amplifies a potential of the selected second bit line.