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Patent US5760445A successfully refreshed from Google Patents.
US5760445A
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Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-03-20
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Granted: 1998-06-02
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Expires: 2017-03-20
Abstract
Abstract A protection device which protects against charge build up on a thin oxide gate during plasma etching is provided. The protection device may be described as a floating well PMOS device. When the PMOS transistor is formed, a lateral parasitic pnp transistor is also formed. In the lateral pnp device the base is floating, the collector is connected to ground and the emitter is connected to the gates of the host PMOS protection device and the device to be protected. In operation, the gate of the PMOS transistor is tied to the source of the PMOS transistor so that the PMOS transistor is off. Thus, the lateral pnp transistor controls the charging and discharging of the charge stored on the gate oxide. Excessive charge build up is prevented by the breakdown voltage of the lateral pnp transistor. Because protection is achieved by pnp breakdown operation, the size of the pnp protection device can be substantially lower than other protection devices.
Inventors
- 👤 Carlos H. Diaz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
180 words
A method for protecting an oxide region of a device during plasma processing, the method comprising the following steps: (a) forming, within a substrate having a first conductivity type, a well region formed in the substrate, the well region having a second opposite conductivity type; (b) forming a gate region over a dielectric region, (c) forming a first region and a second region, the first and second regions having the first conductivity type, the dielectric region being located above the substrate surface between the first and second regions to form a MOS transistor; (d) electrically coupling the gate region and the first region to the oxide region of the device; (e) electrically floating the well region; (f) electrically coupling the substrate to the second region; and, (g) performing a plasma etch, including the following substeps: (g.1) building up charge on the oxide region, and (g.2) before the charge built up in substep (g.1) is sufficient to place a breakdown voltage across the oxide region, turning on the MOS transistor and draining the charge to avoid damage to the oxide region.
Claim 2
Independent Claim
180 words
A method for protecting an oxide region of a device during plasma processing, the method comprising the following steps: (a) forming, within a substrate having a first conductivity type, a well region formed in the substrate, the well region having a second opposite conductivity type; (b) forming a gate region over a dielectric region, (c) forming a first region and a second region, the first and second regions having the first conductivity type, the dielectric region being located above the substrate surface between the first and second regions to form a MOS transistor; (d) electrically coupling the gate region and the first region to the oxide region of the device; (e) electrically floating the well region; (f) electrically coupling the substrate to the second region; and, (g) performing a plasma etch, including the following substeps: (g.1) building up charge on the oxide region, and (g.2) before the charge built up in substep (g.1) is sufficient to place a breakdown voltage across the oxide region, turning on the MOS transistor and draining the charge to avoid damage to the oxide region.
Claim 3
Dependent Claim
16 words
A method as in claim 1 wherein in step (a) the first conductivity type is p-type.
Claim 4
Dependent Claim
23 words
A method as in claim 2 additionally comprising the following step performed before step (g): (h) electrically coupling the second region to ground.
Claim 5
Dependent Claim
16 words
A method as in claim 1 wherein in step (a) the first conductivity type is n-type.
Claim 6
Dependent Claim
26 words
A method as in claim 4 additionally comprising the following step performed before step (g): (h) electrically coupling the second region to a power supply voltage.
Claim 7
Dependent Claim
24 words
A method as in claim 1 wherein in step (g) the oxide region is a gate dielectric region of a second MOS transistor device.
Claim 8
Dependent Claim
21 words
A method as in claim 1 wherein in step (g) the oxide region is a dielectric region of a gate-oxide capacitor.
Claim 9
Dependent Claim
32 words
A method as in claim 1 wherein in step (c) the clamping voltage of the MOS transistor is less than a dielectric breakdown voltage for a device which includes the oxide region.
Claim 10
Dependent Claim
86 words
A method as in claim 1: wherein in step (a) the first conductivity type is p-type; wherein the method additionally comprises the following step performed before step (g): (h) electrically coupling the second region to ground; and, wherein in step (c) the first region of the MOS transistor is also the collector of a lateral pnp device, the well region corresponds to the base of the lateral pnp device, and the second region of the MOS transistor is also the collector of the lateral pnp device.
Claim 11
Dependent Claim
91 words
A method as in claim 1: wherein in step (a) the first conductivity type is n-type; wherein the method additionally comprises the following step performed before step (g): (h) electrically coupling the second region to a power supply voltage; and, wherein in step (c) the first region of the MOS transistor is also the collector of a lateral npn bipolar device, the, well region corresponds to the base of the lateral bipolar device, and the second region of the MOS transistor is also the collector of the lateral npn bipolar device.
Claim 12
Dependent Claim
25 words
A method as in claim 1, wherein in substep (g.2) plasma charging damage to the oxide region is prevented regardless of polarity of the plasma.
Claim 13
Dependent Claim
201 words
A protection device for protecting an oxide region of a device from plasma charging damage while plasma processing during integrated circuit fabrication, the protection device comprising: a substrate having a first conductivity type; a well region formed in the substrate, the well region having a second opposite conductivity type; a first region formed in the well region, the first region having the first conductivity type; a second region formed in the well region, the second region having the first conductivity type; a gate region, the gate region including a dielectric region located above the substrate surface between the first region and the second region to form a MOS transistor; first connector which electrically couples the gate region and the first region to the oxide region; and, second connector which electrically couples the substrate to the second region; wherein with the well region floating, a turn-on voltage of the MOS transistor is sufficiently low so that, when performing a plasma etch where charge is built up on the oxide region, before the charge built up is sufficient to place a breakdown voltage across the oxide region, the MOS transistor turns on and drains the charge to avoid damage to the oxide region.
Claim 14
Dependent Claim
201 words
A protection device for protecting an oxide region of a device from plasma charging damage while plasma processing during integrated circuit fabrication, the protection device comprising: a substrate having a first conductivity type; a well region formed in the substrate, the well region having a second opposite conductivity type; a first region formed in the well region, the first region having the first conductivity type; a second region formed in the well region, the second region having the first conductivity type; a gate region, the gate region including a dielectric region located above the substrate surface between the first region and the second region to form a MOS transistor; first connector which electrically couples the gate region and the first region to the oxide region; and, second connector which electrically couples the substrate to the second region; wherein with the well region floating, a turn-on voltage of the MOS transistor is sufficiently low so that, when performing a plasma etch where charge is built up on the oxide region, before the charge built up is sufficient to place a breakdown voltage across the oxide region, the MOS transistor turns on and drains the charge to avoid damage to the oxide region.
Claim 15
Dependent Claim
14 words
The protection device recited in claim 12 wherein the first conductivity type is p-type.
Claim 16
Dependent Claim
16 words
The protection device recited in claim 13 wherein the second region is electrically coupled to ground.
Claim 17
Dependent Claim
14 words
The protection device recited in claim 12 wherein the first conductivity type is n-type.
Claim 18
Dependent Claim
19 words
The protection device recited in claim 15 wherein the second region is electrically connected to a power supply voltage.
Claim 19
Dependent Claim
27 words
The protection device recited in claim 12 wherein the oxide region to be protected is a gate dielectric region of a MOS transistor device to be protected.
Claim 20
Dependent Claim
22 words
The protection device recited in claim 12 wherein the oxide region to be protected is the oxide region of a gate-oxide capacitor.
Claim 21
Dependent Claim
28 words
The protection device recited in claim 12 wherein the clamping voltage of the protection device is less than the dielectric breakdown voltage of the device to be protected.
Claim 22
Dependent Claim
68 words
The protection device recited in claim 12 wherein: the first conductivity type is p-type; the second region is electrically coupled to ground; and, the first region of the MOS transistor is also the collector of a lateral pnp device, the well region corresponds to the base of the lateral pnp device, and the second region of the MOS transistor is also the collector of the lateral pnp device.
Claim 23
Dependent Claim
74 words
The protection device as recited in claim 12 wherein: the first conductivity type is n-type; the second region is electrically connected to a power supply voltage; and, the first region of the MOS transistor is also the collector of a lateral npn bipolar device, the well region corresponds to the base of the lateral bipolar device, and the second region of the MOS transistor is also the collector of the lateral npn bipolar device.
Claim 24
Dependent Claim
28 words
The protection device as recited in claim 12 wherein the clamp voltage of the protection device can be decreased by reducing the channel length of the MOS transistor.
Claim 25
Dependent Claim
26 words
The protection device as recited in claim 12 wherein the protection device prevents plasma charging damage to the oxide region regardless of polarity of the plasma.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |