US5761078A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field programmable gate arrays using semi-hard multicell macros
Assignee: International Business Machines Corp
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Filing: 1996-03-21
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Granted: 1998-06-02
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Expires: 2016-03-21
Abstract
Abstract A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are "semi-hard" macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function. The router function determines an optimal path to connect the semi-hard macros. Finally, a bitstream is generated from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.
Inventors
- 👤 Christine Marie Fuller
- 👤 Scott Whitney Gould
- 👤 Steven Paul Hartman
- 👤 Eric Ernest Millham
- 👤 Gulsun Yasar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:14
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
197 words
A computer implemented method for automated placement and routing of field programmable gate arrays to achieve optimal timing, comprising the steps of: providing a library of primitives and macros from which a designer can implement a given circuit design, at least some of said macros being semi-hard macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement; creating a logical netlist which contains references to macros and how to connect said macros together to perform a logical function; translating the logical netlist to a physical netlist using a mapper function, the physical netlist for semi-hard macros specifying what is to be connected but not how; finding a best place to put each macro on the field programmable gate array using a placer function, thereby determining an absolute position of the macros; routing direct connections between said macros using a router function, said router function determining an optimal path to connect internal semi-hard macro wiring; and generating a bitstream from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.
Claim 2
Dependent Claim
197 words
A computer implemented method for automated placement and routing of field programmable gate arrays to achieve optimal timing, comprising the steps of: providing a library of primitives and macros from which a designer can implement a given circuit design, at least some of said macros being semi-hard macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement; creating a logical netlist which contains references to macros and how to connect said macros together to perform a logical function; translating the logical netlist to a physical netlist using a mapper function, the physical netlist for semi-hard macros specifying what is to be connected but not how; finding a best place to put each macro on the field programmable gate array using a placer function, thereby determining an absolute position of the macros; routing direct connections between said macros using a router function, said router function determining an optimal path to connect internal semi-hard macro wiring; and generating a bitstream from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.
Claim 3
Dependent Claim
55 words
The computer implemented method for the automated placement and routing of field programmable gate arrays recited in claim 1 further comprising the steps of: providing the designer with an option to route and lock semi-hard macros using said router function; and permitting the designer to route semi-hard macros to ensure optimal performance said semi-hard macros.
Claim 4
Dependent Claim
214 words
A program storage device readable by a machine, tangibly embodying a program of instructions executable by said machine to perform a series of method steps for automated placement and routing of field programmable gate arrays, said method steps comprising: providing a library of primitives and macros from which a designer can implement a given circuit design, at least some of said macros being semi-hard macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement; creating a logical netlist which contains references to macros and how to connect said macros together to perform a logical function; translating the logical netlist to a physical netlist using a mapper function, the physical netlist for semi-hard macros specifying what is to be connected but not how; finding a best place to put each macro on the field programmable gate array using a placer function, thereby determining an absolute position of the macros; routing direct connections between said macros using a router function, said router function determining an optimal path to connect internal semi-hard macro wiring; and generating a bitstream from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.
Claim 5
Dependent Claim
214 words
A program storage device readable by a machine, tangibly embodying a program of instructions executable by said machine to perform a series of method steps for automated placement and routing of field programmable gate arrays, said method steps comprising: providing a library of primitives and macros from which a designer can implement a given circuit design, at least some of said macros being semi-hard macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement; creating a logical netlist which contains references to macros and how to connect said macros together to perform a logical function; translating the logical netlist to a physical netlist using a mapper function, the physical netlist for semi-hard macros specifying what is to be connected but not how; finding a best place to put each macro on the field programmable gate array using a placer function, thereby determining an absolute position of the macros; routing direct connections between said macros using a router function, said router function determining an optimal path to connect internal semi-hard macro wiring; and generating a bitstream from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.
Claim 6
Dependent Claim
51 words
A program storage device readable by machine as in claim 3, wherein said method further comprises the steps of: providing the designer with an option to route and lock semi-hard macros using said router function; and permitting the designer to route semi-hard macros to ensure optimal performance of said semi-hard macros.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |