US5761484A
Expired / Lapsed
US
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Virtual interconnections for reconfigurable logic systems
Assignee: Massachusetts Institute of Technology
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Filing: 1994-04-01
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Granted: 1998-06-02
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Expires: 2014-04-01
Abstract
Abstract A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.
Inventors
- 👤 Anant Agarwal
- 👤 Jonathan Babb
- 👤 Russell Tessier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:20
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
157 words
A reconfigurable electronic system comprising: a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware; inter-module connections between pins of different logic modules; and a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections, a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the configurer determining a static virtual interconnection which includes a communication path extending through an intermediate reprogrammable logic module.
Claim 2
Dependent Claim
157 words
A reconfigurable electronic system comprising: a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware; inter-module connections between pins of different logic modules; and a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections, a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the configurer determining a static virtual interconnection which includes a communication path extending through an intermediate reprogrammable logic module.
Claim 3
Dependent Claim
19 words
A system as claimed in claim 1 wherein each logic module comprises an array of interconnected programmable logic cells.
Claim 4
Dependent Claim
23 words
A system as claimed in claim 1 wherein the configurer configures a logic module to form a multiplexer for communicating through virtual interconnections.
Claim 5
Dependent Claim
31 words
A system as claimed in claim 1 wherein the logic modules are configured to operate in phases within a target clock period with the inter-module communications being performed within each phase.
Claim 6
Dependent Claim
25 words
A system as claimed in claim 4 wherein the configurer optimizes logic module selection and phase division of the target circuit based on inter-module dependencies.
Claim 7
Dependent Claim
62 words
A system as claimed in claim 4 wherein the target clock period is a clock period of the target circuit which dictates the maximum rate at which signal lines of the target circuit change value and wherein each target clock period comprises a plurality of system clock periods which dictate the maximum rate at which signals in the electronic system change value.
Claim 8
Dependent Claim
18 words
A system as claimed in claim 1, including asynchronous logic hardwired to dedicated pins of the logic modules.
Claim 9
Dependent Claim
19 words
A system as claimed in claim 1 wherein data is accessed from memory elements external to the logic modules.
Claim 10
Dependent Claim
21 words
A system as claimed in claim 8 wherein there are time multiplexed interconnections between the logic modules and the memory elements.
Claim 11
Dependent Claim
17 words
A system as claimed in claim 1 wherein the logic modules are Field Programmable Gate Arrays (FPGAs).
Claim 12
Dependent Claim
15 words
A system as claimed in claim 1 wherein each logic module is a single chip.
Claim 13
Dependent Claim
20 words
A system as claimed in claim 1 wherein the digital system is an emulation system for emulating the target system.
Claim 14
Dependent Claim
19 words
A system as claimed in claim 1 wherein logic modules are configured to include pins dedicated to individual signals.
Claim 15
Dependent Claim
29 words
A logic system as claimed in claim 1 wherein the configurer comprises a partitioner for partitioning the target logic circuit, each partition being configured into a respective logic module.
Claim 16
Dependent Claim
50 words
A system as claimed in claim 14 further comprising a dependency analyzer and a divider for dividing a target clock period into phases during which program logic functions are performed and signals are transmitted between the logic modules, the phase division being a function of partition dependencies and memory assignments.
Claim 17
Dependent Claim
27 words
A system as claimed in claim 14 further comprising a router for configuring the logic modules to route signals between logic modules through intermediate reprogrammable logic modules.
Claim 18
Dependent Claim
155 words
A reconfigurable electronic system comprising: a plurality of reprogrammable logic modules, each logic module having an array of gates reconfigurable to define a hardware logic circuit and a plurality of pins for communicating signals external to the logic module; inter-module connections between pins of different logic modules; and a configurer for automatically configuring the array of gates, each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and gates of the logic module of the partition being configured as a multiplexer for receiving a plurality of outputs from the configured array of gates and for statically communicating the received outputs through a single pin in a multiplexed, pipelined fashion.
Claim 19
Dependent Claim
155 words
A reconfigurable electronic system comprising: a plurality of reprogrammable logic modules, each logic module having an array of gates reconfigurable to define a hardware logic circuit and a plurality of pins for communicating signals external to the logic module; inter-module connections between pins of different logic modules; and a configurer for automatically configuring the array of gates, each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and gates of the logic module of the partition being configured as a multiplexer for receiving a plurality of outputs from the configured array of gates and for statically communicating the received outputs through a single pin in a multiplexed, pipelined fashion.
Claim 20
Dependent Claim
23 words
A system as claimed in claim 17 further comprising at least one shift register coupled between the multiplexer and the configured gate array.
Claim 21
Dependent Claim
19 words
A system as claimed in claim 18 wherein the shift registers are configured from gates in the logic module.
Claim 22
Dependent Claim
150 words
A reconfigurable electronic system comprising: a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware; inter-module connections between pins of different logic modules; and a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections, a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through static virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the electronic system including dedicated pins for providing a predetermined signal.
Claim 23
Dependent Claim
150 words
A reconfigurable electronic system comprising: a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals external to the logic module and a plurality of logic elements for implementing logic in hardware; inter-module connections between pins of different logic modules; and a configurer for automatically configuring each logic module to define a partition of a specified target circuit with communications between the partitions of the target circuit being provided through pins and inter-module connections, a partition of the configured system having a number of inter-module communications to other partitions that exceeds the number of pins on the logic module of the partition and the logic module of the partition being configured to communicate through static virtual interconnections in a time-multiplexed fashion through at least one pin of the logic module of the partition, the electronic system including dedicated pins for providing a predetermined signal.
Claim 24
Independent Claim
97 words
A method of automatically compiling a reconfigurable digital system, comprising the steps of: partitioning a target circuit into a plurality of partitions, each partition to be configured into a reprogrammable logic module having a plurality of pins and a plurality of logic elements; configuring the logic modules to create partitions of the target circuit; determining static virtual interconnections between partitions corresponding to at least one common pin with signals along the virtual interconnections being time-multiplexed through the at least one common pin; and configuring the logic modules to route signals between logic modules through intermediate logic modules.
Claim 25
Independent Claim
97 words
A method of automatically compiling a reconfigurable digital system, comprising the steps of: partitioning a target circuit into a plurality of partitions, each partition to be configured into a reprogrammable logic module having a plurality of pins and a plurality of logic elements; configuring the logic modules to create partitions of the target circuit; determining static virtual interconnections between partitions corresponding to at least one common pin with signals along the virtual interconnections being time-multiplexed through the at least one common pin; and configuring the logic modules to route signals between logic modules through intermediate logic modules.
Claim 26
Dependent Claim
48 words
A method as claimed in claim 21 further comprising the step of dividing a first clock period which dictates the maximum rate at which signal lines within the target circuit change value into phases during which program logic functions are performed and signals are transmitted between logic modules.
Claim 27
Dependent Claim
56 words
A reconfigurable logic module comprising: an array of gates configurable to define a logic circuit; and a virtual interconnection comprising a plurality of gates reconfigured as a multiplexer, the multiplexer receiving a plurality of outputs from the configured gate array and communicating each of the received outputs through a single pin in a multiplexed, pipelined fashion.
Claim 28
Dependent Claim
56 words
A reconfigurable logic module comprising: an array of gates configurable to define a logic circuit; and a virtual interconnection comprising a plurality of gates reconfigured as a multiplexer, the multiplexer receiving a plurality of outputs from the configured gate array and communicating each of the received outputs through a single pin in a multiplexed, pipelined fashion.
Claim 29
Dependent Claim
23 words
A logic module as claimed in claim 23 further comprising at least one register coupled between the multiplexer and the configured gate array.
Claim 30
Dependent Claim
22 words
A logic module as claimed in claim 24 wherein the at least one register is configured from gates in the logic module.
Claim 31
Dependent Claim
18 words
A logic module as claimed in claim 24 wherein the at least one register includes a shift register.
Claim 32
Dependent Claim
19 words
A logic module as claimed in claim 23 wherein the logic module is a Field Programmable Gate Array (FPGA).
Claim 33
Dependent Claim
83 words
A reconfigurable electronic system comprising a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals between logic modules; and a configurer to configure each logic module to define a partition of a specified target circuit, a partition of the configured target circuit having a number of interconnections to other partitions that exceeds the number of pins on the logic module and the logic module being configured to communicate through virtual interconnections through at least one pin.
Claim 34
Dependent Claim
83 words
A reconfigurable electronic system comprising a plurality of reprogrammable logic modules, each logic module having a plurality of pins for communicating signals between logic modules; and a configurer to configure each logic module to define a partition of a specified target circuit, a partition of the configured target circuit having a number of interconnections to other partitions that exceeds the number of pins on the logic module and the logic module being configured to communicate through virtual interconnections through at least one pin.
Claim 35
Dependent Claim
23 words
A system as claimed in claim 28 wherein the configurer configures a logic module to form a multiplexer for communicating through virtual interconnections.
Claim 36
Dependent Claim
34 words
A system as claimed in claim 28 wherein pins of logic modules are directly connected to pins of other logic modules and routing of signals between the logic modules is through intermediate logic modules.
Claim 37
Dependent Claim
14 words
A system as claimed in claim 28 wherein the logic modules comprise hardwired multiplexers.
Claim 38
Dependent Claim
25 words
A system as claimed in claim 28 wherein the configurer optimizes logic module selection and phase division of the target circuit based on interpartition dependencies.
Claim 39
Dependent Claim
19 words
A system as claimed in claim 28 wherein data is accessed from memory elements external to the logic modules.
Claim 40
Dependent Claim
17 words
A system as claimed in claim 28 wherein the logic modules are Field Programmable Gate Arrays (FPGAs).
Claim 41
Dependent Claim
19 words
A system as claimed in claim 28 wherein the system is an emulation system for emulating the target circuit.
Claim 42
Dependent Claim
33 words
A system as claimed in claim 28 further comprising inter-module connections between pins of different logic modules with interconnections between the partitions of the target circuit being provided through pins and inter-module connections.
Claim 43
Dependent Claim
20 words
A system as claimed in claim 36 wherein the inter-module communications include interconnections which extend through intermediate reconfigurable logic modules.
Claim 44
Dependent Claim
30 words
A system as claimed in claim 28 wherein the logic modules are configured to operate in phases within a target clock period with inter-module communications being performed within each phase.
Claim 45
Dependent Claim
22 words
A system as claimed in claim 28 wherein the logic module is configured to communicate through virtual interconnections in a time-multiplexed fashion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |