External parallel-port device using a timer to measure and adjust data transfer rate

Claim 1

An external device for connection to a parallel port of a personal computer (PC), the external device comprising: a parallel-port connector for connecting to a parallel-port cable connected to the parallel port of the PC; a data register, connected to the parallel-port connector, for storing data transferred from the PC to the external device; a control register, connected to the parallel-port connector, for buffering control signals including a first control signal from the PC to the external device; a status register, connected to the parallel-port connector, for driving status signals from the external device to the PC; controller means, coupled to the data register, the control register, and the status register, for receiving data and commands from the PC to the external device; an external timer, coupled to the controller means, for timing the first control signal from the control register, the external timer triggered by a first edge of the first control signal and halted by a second edge of the first control signal, the external timer outputting a count value in a digital format indicating an amount of time from the first edge to the second edge of the first control signal; wherein the controller means further comprises transfer means for reading the count value in the digital format from the external timer and transferring the count value to the parallel port of the PC; compare means for comparing the count value in the digital format to a target count value, the target count value being proportional to a target pulse width for the first control signal; and extension means, in the PC and responsive to the compare means, for extending a period of time between the first edge and the second edge of the first control signal, whereby the external timer in the external device measures a pulse width of the first control signal from the parallel port of the PC and wherein the pulse width of the first control signal is extended when the compare means indicates that the count value is less than the target count value.

Claim 10

A method of determining the speed of an AT bus on a personal computer (PC) and adjusting timing of a first control signal for controlling data transfer on a parallel port on the PC, the method comprising: (a) reading an internal timer on the PC for a first count value and storing the first count value; (b) accessing a parallel-port register on the AT bus, the parallel-port register including a cell which drives the first control signal on the parallel port; (c) executing a loop of n delay instructions; (d) repeating in sequence steps (b) and (c) for a predetermined number of iterations; (e) reading the internal timer on the PC for a second count value; (f) obtaining the difference between the first count value and the second count value, the difference being an elapsed count; (g) comparing the elapsed count to a target count, the target count being for a target elapsed time period for accessing the parallel-port register; (h) when the elapsed count is less than the target count, increasing a number n of delay instructions in the loop of n delay instructions and repeating steps (a) through (g) in sequence; (i) when the elapsed count is not less than the target count, saving the number n of delay instructions in the loop of n delay instructions and executing the loop of n delay instructions after each access of the parallel-port register, whereby accessing of the parallel-port register is tested and adjusted to meet the target elapsed time period.

Claim 11

A method of determining the speed of an AT bus on a personal computer (PC) and adjusting timing of a first control signal for controlling data transfer on a parallel port on the PC, the method comprising: (a) reading an internal timer on the PC for a first count value and storing the first count value; (b) accessing a parallel-port register on the AT bus, the parallel-port register including a cell which drives the first control signal on the parallel port; (c) executing a loop of n delay instructions; (d) repeating in sequence steps (b) and (c) for a predetermined number of iterations; (e) reading the internal timer on the PC for a second count value; (f) obtaining the difference between the first count value and the second count value, the difference being an elapsed count; (g) comparing the elapsed count to a target count, the target count being for a target elapsed time period for accessing the parallel-port register; (h) when the elapsed count is less than the target count, increasing a number n of delay instructions in the loop of n delay instructions and repeating steps (a) through (g) in sequence; (i) when the elapsed count is not less than the target count, saving the number n of delay instructions in the loop of n delay instructions and executing the loop of n delay instructions after each access of the parallel-port register, whereby accessing of the parallel-port register is tested and adjusted to meet the target elapsed time period.