US5771359A
Expired / Lapsed
US
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Bridge having a data buffer for each bus master
Assignee: Hewlett Packard Development Co LP
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Filing: 1995-10-13
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Granted: 1998-06-23
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Expires: 2015-10-13
Abstract
Abstract A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The bridge includes master and slave capability on both buses and an arbiter for selecting between requests from bus masters on one bus. The data buffer includes a number of dual ported memories for write posting and read ahead operations. Each dual ported memory is allocated to a bus master of the one bus. The bridge allows data operations to each dual ported memory based on data or space availability of the memory. Simultaneous reading and writing capability on alternate buses is provided.
Inventors
- 👤 William C. Galloway
- 👤 Ryan A. Callison
- 👤 Gregory T. Chandler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; G06F13/4059
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
138 words
A bridge for coupling a first bus to a second bus, the first bus capable of having a plurality of bus masters for performing read and write oprations to devices on the second bus, each bus master providing a bus access request to access to the first bus, the bridge comprising: a first bus interface; a second bus interface; a plurality of data buffers coupled to said first and second bus interfaces, said plurality of data buffers for storing data transferred between the buses, each data buffer of said plurality of data buffers corresponding to a different one of said plurality of bus masters; and an arbiter for selecting between the bus access requests received from the bus masters and for providing a bus grant to a selected bus master based on availability of a corresponding data buffer.
Claim 2
Dependent Claim
138 words
A bridge for coupling a first bus to a second bus, the first bus capable of having a plurality of bus masters for performing read and write oprations to devices on the second bus, each bus master providing a bus access request to access to the first bus, the bridge comprising: a first bus interface; a second bus interface; a plurality of data buffers coupled to said first and second bus interfaces, said plurality of data buffers for storing data transferred between the buses, each data buffer of said plurality of data buffers corresponding to a different one of said plurality of bus masters; and an arbiter for selecting between the bus access requests received from the bus masters and for providing a bus grant to a selected bus master based on availability of a corresponding data buffer.
Claim 3
Dependent Claim
40 words
The bridge of claim 1, wherein said plurality of data buffers each provide a ready indication to said first bus interface based on said data buffer being empty during a data read operation or full during a data write operation.
Claim 4
Dependent Claim
46 words
The bridge of claim 2, wherein the bridge is capable of being a bus master on the first bus and wherein the bridge provides a bus access request to said arbiter and a data buffer in the bridge is not provided for said bridge bus master.
Claim 5
Dependent Claim
23 words
The bridge of claim 3, wherein said first bus interface terminates said data operation if the bridge requests access to the first bus.
Claim 6
Dependent Claim
27 words
The bridge of claim 1, wherein each data buffer corresponds to one of the bus masters based on the bus access request provided by the bus master.
Claim 7
Dependent Claim
62 words
The bridge of claim 1, wherein said plurality of data buffers each provide a ready indication to said second bus interface based on said data buffer being empty during a data read operation or full during a data write operation, and wherein said second bus interface requests access to the second bus if any of said plurality of data buffers are ready.
Claim 8
Dependent Claim
28 words
The bridge of claim 1, wherein the first bus is a peripheral component interconnect (PCI) bus and the second bus is an extended industry standard architecture (EISA) bus.
Claim 9
Dependent Claim
17 words
The bridge of claim 1, wherein the first and second buses are peripheral component interconnect (PCI) buses.
Claim 10
Dependent Claim
155 words
A computer system, comprising: a first bus; a second bus; and a bridge coupled to said first and second buses for providing communications between said first and second buses, said first bus capable of having a plurality of bus masters for performing read and write operations to devices on said second bus, each bus master providing a bus access request to access to said first bus, the bridge comprising: a first bus interface; a second bus interface; and a plurality of data buffers coupled to said first and second bus interfaces, said plurality of data buffers for storing data transferred between the first and second buses, each data buffer of said plurality of data buffers corresponding to a different bus master; and an arbiter for selecting between the bus access requests received from the bus masters and for providing a bus grant to a selected bus master based on availability of a corresponding data buffer.
Claim 11
Dependent Claim
155 words
A computer system, comprising: a first bus; a second bus; and a bridge coupled to said first and second buses for providing communications between said first and second buses, said first bus capable of having a plurality of bus masters for performing read and write operations to devices on said second bus, each bus master providing a bus access request to access to said first bus, the bridge comprising: a first bus interface; a second bus interface; and a plurality of data buffers coupled to said first and second bus interfaces, said plurality of data buffers for storing data transferred between the first and second buses, each data buffer of said plurality of data buffers corresponding to a different bus master; and an arbiter for selecting between the bus access requests received from the bus masters and for providing a bus grant to a selected bus master based on availability of a corresponding data buffer.
Claim 12
Dependent Claim
41 words
The computer system of claim 9, wherein said plurality of data buffers each provide a ready indication to said first bus interface based on said data buffer being empty during a data read operation or full during a data write operation.
Claim 13
Dependent Claim
47 words
The computer system of claim 10, wherein said bridge is capable of being a bus master on said first bus and wherein said bridge provides a bus access request to said arbiter and a data buffer in said bridge is not provided for said bridge bus master.
Claim 14
Dependent Claim
24 words
The computer system of claim 11, wherein said first bus interface terminates said data operation if said bridge requests access to the first bus.
Claim 15
Dependent Claim
28 words
The computer system of claim 9, wherein each data buffer corresponds to one of the bus masters based on the bus access request provided by the bus master.
Claim 16
Dependent Claim
63 words
The computer system of claim 9, wherein said plurality of data buffers each provide a ready indication to said second bus interface based on said data buffer being empty during a data read operation or full during a data write operation, and wherein said second bus interface requests access to said second bus if any of said plurality of data buffers is ready.
Claim 17
Dependent Claim
29 words
The computer system of claim 9, wherein said first bus is a peripheral component interconnect (PCI) bus and said second bus is an extended industry standard architecture (EISA) bus.
Claim 18
Dependent Claim
18 words
The computer system of claim 9, wherein said first and second buses are peripheral component interconnect (PCI) buses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-22 | 2001-12-22 | 2002-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-22 | 2005-12-22 | 2006-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-22 | 2009-12-22 | 2010-06-23 | $7700.00 | Window Closed / Lapsed |