PCI bus to target integrated circuit interconnect mechanism allowing multiple bus masters and two different protocols on the same bus

Claim 2

A computer system, comprising: a first expansion bus which operates according to a first transfer protocol, wherein the first expansion bus is adapted to couple to one or more peripheral devices; a central processing unit operatively coupled to the first expansion bus; a bus bridge coupled to the first expansion bus; a second bus coupled to the bus bridge, wherein the second bus includes a second transfer protocol; at least one peripheral device of a first type coupled to the second bus, wherein the at least one peripheral device of the first type is compatible with the second transfer protocol of the second bus; and at least one peripheral device of a second type coupled to the second bus, wherein the at least one peripheral device of the second type is compatible with a third transfer protocol of a peripheral bus standard, the third transfer protocol of the peripheral bus standard being different from the second transfer protocol of the second bus; wherein the bus bridge is operable to convert signals between the first expansion bus and the second bus, wherein the bus bridge is operable to implement the second transfer protocol on the second bus, wherein the bus bridge is also operable to implement the third transfer protocol of the peripheral bus standard on the second bus; wherein the bus bridge is configured to communicate with the at least one peripheral device of the first type using the second transfer protocol of the second bus, and the bus bridge is configured to communicate with the at least one peripheral device of the second type using the third transfer protocol of the peripheral bus standard.

Claim 3

The computer system of claim 1, further comprising: an adapter card coupled to the first bus; wherein the bus bridge, the second bus, the at least one peripheral device of the first type, and the at least one peripheral device of the second type are comprised on the adapter card.

Claim 4

The computer system of claim 1, further including a logic circuit at least partially interposed between the bus bridge and the at least one peripheral device of the second type, the logic circuit configured to receive address signals corresponding to the third transfer protocol of the peripheral bus standard.

Claim 5

The computer system of claim 1, wherein the first expansion bus is a Peripheral Component Interface bus and the first transfer protocol is a Peripheral Component Interface Standard protocol.

Claim 6

The computer system of claim 1, wherein the peripheral bus standard bus is an Industry Standard Architecture (ISA) AT bus and the third transfer protocol is an Industry Standard Architecture AT bus protocol.

Claim 7

The computer system of claim 1, wherein the first transfer protocol is the same as the second transfer protocol.

Claim 8

The computer system of claim 1, wherein the at least one peripheral device of the first type comprises at least one destination port for receiving data transmissions from the bus bridge on the second bus using the second transfer protocol; and wherein the bus bridge comprises: a transceiver configured to interface data transmissions on the second bus using the second transfer protocol; and at least one transmit port operatively coupled to the transceiver, the at least one transmit port comprising: a data buffer for receiving data to be transmitted over the second bus; and a transmit port state machine coupled to the data buffer and configured to identify a destination port address of the at least one destination port on the at least one peripheral device of the first type for receiving data transmissions from the bus bridge on the second bus using the second transfer protocol.

Claim 9

The computer system of claim 7, wherein the transmit port state machine further comprises a transmit port control register for storing the destination port address.

Claim 10

The computer system of claim 8, wherein data will be transmitted over the second bus if a bit in the transmit port control register has been set.

Claim 11

The computer system of claim 7, wherein the bus bridge further comprises: at least one receive port operatively coupled to the transceiver, the at least one receive port comprising: a receive data buffer for receiving data that has been transmitted from the at least one peripheral device of the first type over the second bus; and a receive port state machine coupled to the receive data buffer, the receive port state machine including a receive control register, wherein the receive data buffer receives data that has been transmitted over the second bus if a bit in the receive control register has been set.

Claim 12

The computer system of claim 10, wherein the receive port state machine is further configured to request a data transfer if the receive data buffer is empty.

Claim 13

A bus bridge for coupling to a first bus and for interfacing the first bus to a second bus, the bus bridge comprising: a first bus port for coupling to a first expansion bus, wherein the first bus implements a first transfer protocol compatible with the first bus port, wherein the first bus port is adapted to couple through the first expansion bus to one or more peripheral devices; a second bus port for coupling to a second bus, wherein the second bus implements a second transfer protocol compatible with the second bus port, wherein the second bus port is adapted to couple through the second bus to one or more peripheral devices; wherein the bus bridge is operable to implement the second transfer protocol on the second bus to communicate with one or more peripheral devices of a first type coupled to the second bus which are compatible with the second transfer protocol of the second bus, and wherein the bus bridge is operable to implement a third transfer protocol on the second bus to communicate with one or more peripheral devices of a second type coupled to the second bus which are compatible with a third transfer protocol of a peripheral bus standard, the third transfer protocol of the peripheral bus standard being different from the second transfer protocol of the second bus.

Claim 14

A bus bridge for coupling to a first bus and for interfacing the first bus to a second bus, the bus bridge comprising: a first bus port for coupling to a first expansion bus, wherein the first bus implements a first transfer protocol compatible with the first bus port, wherein the first bus port is adapted to couple through the first expansion bus to one or more peripheral devices; a second bus port for coupling to a second bus, wherein the second bus implements a second transfer protocol compatible with the second bus port, wherein the second bus port is adapted to couple through the second bus to one or more peripheral devices; wherein the bus bridge is operable to implement the second transfer protocol on the second bus to communicate with one or more peripheral devices of a first type coupled to the second bus which are compatible with the second transfer protocol of the second bus, and wherein the bus bridge is operable to implement a third transfer protocol on the second bus to communicate with one or more peripheral devices of a second type coupled to the second bus which are compatible with a third transfer protocol of a peripheral bus standard, the third transfer protocol of the peripheral bus standard being different from the second transfer protocol of the second bus.

Claim 15

The bus bridge of claim 12, wherein the first bus is a Peripheral Component Interface bus and the first transfer protocol is a Peripheral Component Interface Standard protocol.

Claim 16

The bus bridge of claim 12, wherein the peripheral bus standard bus is an Industry Standard Architecture and the third transfer protocol is an Industry Standard Architecture protocol.

Claim 17

The bus bridge of claim 12, wherein the first transfer protocol is the same as the second transfer protocol.

Claim 18

The bus bridge of claim 12, further comprising a transceiver operatively coupled to the second bus port configured to interface data transmissions on the second bus using the second transfer protocol.

Claim 19

The bus bridge of claim 12, wherein the second bus port comprises: a transmit data buffer for receiving data to be transmitted over the second bus; and a transmit port state machine coupled to the transmit data buffer and configured to identify a destination port address of a destination port on the one or more peripheral devices of the first type on the second bus using the second transfer protocol.

Claim 20

The bus bridge of claim 17, wherein the transmit port state machine further comprises a transmit port control register for storing the destination port address.

Claim 21

The bus bridge of claim 18, wherein data will be transmitted over the second bus if a bit in the transmit port control register has been set.

Claim 22

The bus bridge of claim 12, wherein the second bus port comprises: a receive data buffer for receiving data that has been transmitted from the one or more peripheral devices of the first type over the second bus; and a receive port state machine coupled to the receive data buffer, the receive port state machine including a receive control register, wherein the receive data buffer receives data that has been transmitted over the second bus if a bit in the receive control register has been set.

Claim 23

The bus bridge of claim 20, wherein the receive port state machine is further configured to request a data transfer if the receive data buffer is empty.

Claim 24

A computer system, comprising: a first expansion bus which operates according to a first transfer protocol, wherein the first expansion bus is adapted to couple to one or more peripheral devices; a central processing unit operatively coupled to the first expansion bus; and an adapter card coupled to the first expansion bus, wherein the adapter card comprises: a bus bridge coupled to the first expansion bus; a second bus coupled to the bus bridge, wherein the second bus includes a second transfer protocol; at least one peripheral device of a first type coupled to the second bus, wherein the at least one peripheral device of the first type is compatible with the second transfer protocol of the second bus; and at least one peripheral device of a second type coupled to the second bus, wherein the at least one peripheral device of the second type is compatible with a third transfer protocol of a peripheral bus standard, the third transfer protocol of the peripheral bus standard being different from the second transfer protocol of the second bus; wherein the bus bridge is operable to convert signals between the first expansion bus and the second bus, wherein the bus bridge is operable to implement the second transfer protocol on the second bus, wherein the bus bridge is also operable to implement the third transfer protocol of the peripheral bus standard on the second bus; wherein the bus bridge is configured to communicate with the at least one peripheral device of the first type using the second transfer protocol of the second bus, and the bus bridge is configured to communicate with the at least one peripheral device of the second type using the third transfer protocol of the peripheral bus standard.

Claim 25

A computer system, comprising: a first expansion bus which operates according to a first transfer protocol, wherein the first expansion bus is adapted to couple to one or more peripheral devices; a central processing unit operatively coupled to the first expansion bus; and an adapter card coupled to the first expansion bus, wherein the adapter card comprises: a bus bridge coupled to the first expansion bus; a second bus coupled to the bus bridge, wherein the second bus includes a second transfer protocol; at least one peripheral device of a first type coupled to the second bus, wherein the at least one peripheral device of the first type is compatible with the second transfer protocol of the second bus; and at least one peripheral device of a second type coupled to the second bus, wherein the at least one peripheral device of the second type is compatible with a third transfer protocol of a peripheral bus standard, the third transfer protocol of the peripheral bus standard being different from the second transfer protocol of the second bus; wherein the bus bridge is operable to convert signals between the first expansion bus and the second bus, wherein the bus bridge is operable to implement the second transfer protocol on the second bus, wherein the bus bridge is also operable to implement the third transfer protocol of the peripheral bus standard on the second bus; wherein the bus bridge is configured to communicate with the at least one peripheral device of the first type using the second transfer protocol of the second bus, and the bus bridge is configured to communicate with the at least one peripheral device of the second type using the third transfer protocol of the peripheral bus standard.

Claim 26

The computer system of claim 22, further including a logic circuit at least partially interposed between the bus bridge and the at least one peripheral device of the second type, the logic circuit configured to receive address signals corresponding to the third transfer protocol of the peripheral bus standard.

Claim 27

The computer system of claim 22, wherein the first expansion bus is a Peripheral Component Interface bus and the first transfer protocol is a Peripheral Component Interface Standard protocol.

Claim 28

The computer system of claim 22, wherein the peripheral bus standard bus is an Industry Standard Architecture (ISA) AT bus and the third transfer protocol is an Industry Standard Architecture AT bus protocol.

Claim 29

The computer system of claim 22, wherein the first transfer protocol is the same as the second transfer protocol.