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US5777922A
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Flash memory device
Assignee: SK Hynix Inc
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Filing: 1996-10-18
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Granted: 1998-07-07
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Expires: 2016-10-18
Abstract
Abstract The present invention provides a flash memory device wherein memory cells in each of the memory cell blocks are divided into a plurality of memory cell groups. In each memory cell group, local bit lines are laid out connected by segmentation transistors. When selecting a memory cell, only a local bit line connected to a memory cell selected by an operation of the segmentation transistor is coupled to a global bit line so that the load to be applied to the bit lines is minimized during the read out operation.
Inventors
- 👤 Young Jung Choi
- 👤 Joo Weon Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:00
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
125 words
A flash memory device comprising: a plurality of memory cell groups having a plurality of local bit lines and word lines which are arranged in the form of a matrix; a pair of segmentation transistors connecting corresponding local bit lines between two memory cell groups; a plurality of connection nodes formed by the connecting of corresponding local bit lines by said pair of segmentation transistors; a row address buffer which generates an address signal; a pre-decoder which generates a pre-decoded signal by pre-decoding said address signal; a segmentation signal generator to selectively turn on said segmentation transistors, wherein said segmentation signal generator operates in response to said pre-decoded signal; and a plurality of global bit lines connected to corresponding connection nodes of said segmentation transistors.
Claim 2
Dependent Claim
125 words
A flash memory device comprising: a plurality of memory cell groups having a plurality of local bit lines and word lines which are arranged in the form of a matrix; a pair of segmentation transistors connecting corresponding local bit lines between two memory cell groups; a plurality of connection nodes formed by the connecting of corresponding local bit lines by said pair of segmentation transistors; a row address buffer which generates an address signal; a pre-decoder which generates a pre-decoded signal by pre-decoding said address signal; a segmentation signal generator to selectively turn on said segmentation transistors, wherein said segmentation signal generator operates in response to said pre-decoded signal; and a plurality of global bit lines connected to corresponding connection nodes of said segmentation transistors.
Claim 3
Dependent Claim
124 words
A flash memory device comprising: a plurality of memory cell groups having a plurality of local bit lines and word lines which are arranged in the form of a matrix; a pair of segmentation transistors connecting corresponding local bit lines between two memory cell groups; a plurality of connection nodes formed by the connecting of corresponding local bit lines by said pair of segmentation transistors; a pre-decoder which generates a pre-decoded signal; a row decoder which generates an output signal based on said pre-decoded signal; a segmentation signal generator to selectively turn on said segmentation transistors, wherein said segmentation signal generator operates in response to said output signal; and a plurality of global bit lines connected to corresponding connection node of said segmentation transistors.
Claim 4
Dependent Claim
124 words
A flash memory device comprising: a plurality of memory cell groups having a plurality of local bit lines and word lines which are arranged in the form of a matrix; a pair of segmentation transistors connecting corresponding local bit lines between two memory cell groups; a plurality of connection nodes formed by the connecting of corresponding local bit lines by said pair of segmentation transistors; a pre-decoder which generates a pre-decoded signal; a row decoder which generates an output signal based on said pre-decoded signal; a segmentation signal generator to selectively turn on said segmentation transistors, wherein said segmentation signal generator operates in response to said output signal; and a plurality of global bit lines connected to corresponding connection node of said segmentation transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |