Method of fabricating a semiconductor read-only memory device for permanent storage of multi-level coded data

Claim 1

A method for fabricating a semiconductor ROM device for permanent storage of multi-level coded data, comprising the steps of: (1) preparing a semiconductor substrate; (2) forming a plurality of polysilicon layers serving as a plurality of major gate structures on the substrate; then forming a plurality of sidewall spacers respectively on the sidewalls of the plurality of major gate structures; (3) forming a plurality of polysilicon layers respectively between each neighboring pair of the major gate structures to serve as a plurality of minor gate structures; the plurality of major gate structures and the minor gate structures therebetween in combination being associated with a plurality of memory cells for the ROM device, with each memory including one major gate structure and one neighboring minor gate structure; (4) forming a dielectric layer over the memory cells; (5) from the memory cells of the ROM device, locating a first selected group of the memory cells that are to be set to a first logic state, a second selected group of the memory cells that are to be set to a second logic state, a third selected group of the memory cells that are to be set to a third logic state, and a fourth selected group of the memory cells that are to be set to a fourth logic state; then performing a mask-programming process so as to form a plurality of contact windows in the dielectric layer in such a manner that the contact windows expose all of the major gate structures that are associated with the first selected group of the memory cells, all of the minor gate structures that are associated with the second selected group of the memory cells, and all of the sidewall spaces and part of the abutting major and minor gate structures that are associated with the third group of memory cells, with all of the major and minor gate structures that are associated with the fourth selected group of the memory cells being isolated by the dielectric layer; (6) forming a conductive layer over the dielectric layer, the conductive layer filling up all of the contact windows; and (7) removing selected portions of the conductive layer so as to form a plurality of substantially parallel-spaced word lines.

Claim 2

A method for fabricating a semiconductor ROM device for permanent storage of multi-level coded data, comprising the steps of: (1) preparing a semiconductor substrate; (2) forming a plurality of polysilicon layers serving as a plurality of major gate structures on the substrate; then forming a plurality of sidewall spacers respectively on the sidewalls of the plurality of major gate structures; (3) forming a plurality of polysilicon layers respectively between each neighboring pair of the major gate structures to serve as a plurality of minor gate structures; the plurality of major gate structures and the minor gate structures therebetween in combination being associated with a plurality of memory cells for the ROM device, with each memory including one major gate structure and one neighboring minor gate structure; (4) forming a dielectric layer over the memory cells; (5) from the memory cells of the ROM device, locating a first selected group of the memory cells that are to be set to a first logic state, a second selected group of the memory cells that are to be set to a second logic state, a third selected group of the memory cells that are to be set to a third logic state, and a fourth selected group of the memory cells that are to be set to a fourth logic state; then performing a mask-programming process so as to form a plurality of contact windows in the dielectric layer in such a manner that the contact windows expose all of the major gate structures that are associated with the first selected group of the memory cells, all of the minor gate structures that are associated with the second selected group of the memory cells, and all of the sidewall spaces and part of the abutting major and minor gate structures that are associated with the third group of memory cells, with all of the major and minor gate structures that are associated with the fourth selected group of the memory cells being isolated by the dielectric layer; (6) forming a conductive layer over the dielectric layer, the conductive layer filling up all of the contact windows; and (7) removing selected portions of the conductive layer so as to form a plurality of substantially parallel-spaced word lines.

Claim 7

A method for fabricating a semiconductor ROM device for permanent storage of multi-level coded data, comprising the steps of: (1) preparing a semiconductor substrate; (2) forming a gate oxide layer over the substrate, and then forming a first polysilicon layer over the gate oxide layer; (3) removing selected portions of the first polysilicon layer to expose selected surface areas of the gate oxide layer; (4) performing an ion-implantation process through the exposed areas of the gate oxide layer so as to form a plurality of source/drain regions in the substrate, the source/drain regions serving as a plurality of bit lines for the ROM device; (5) removing selected portions of the remaining portions of the first polysilicon layer so as to an array of major gate structures on the substrate; (6) forming a plurality of sidewall spacers respectively on the sidewalls of the plurality of major gate structures; (7) forming a plurality of second polysilicon layers respectively between each neighboring pair of the major gate structures to serve as a plurality of minor gate structures; the plurality of major gate structures and the minor gate structure therebetween in combination being associated with a plurality of memory cells for the ROM device, with each memory cell including one major gate structure and one neighboring minor gate structure; (8) forming a dielectric layer over the memory cells; (9) from the memory cells of the ROM device, locating a first selected group of the memory cells that are to be set to a first logic state, a second selected group of the memory cells that are to be set to a second logic state, a third selected group of the memory cells that are to be set to a third logic state, and a fourth selected group of the memory cells that are to be set to a fourth logic state; then performing a mask-programming process so as to form a plurality of contact windows in the dielectric layer in such a manner that the contact windows expose all of the major gate structures that are associated with the first selected group of the memory cells, all of the minor gate structures that are associated with the second selected group of the memory cells, and all of the sidewall spaces and part of the abutting major and minor gate structures that are associated with the third group of memory cells, with all of the major and minor gate structures that are associated with the fourth selected group of the memory cells being isolated by the dielectric layer; (10) forming a conductive layer over the dielectric layer, the conductive layer filling up all of the contact windows in the dielectric layer; and (11) removing selected portions of the conductive layer so as to form a plurality of substantially parallel-spaced word lines.

Claim 8

A method for fabricating a semiconductor ROM device for permanent storage of multi-level coded data, comprising the steps of: (1) preparing a semiconductor substrate; (2) forming a gate oxide layer over the substrate, and then forming a first polysilicon layer over the gate oxide layer; (3) removing selected portions of the first polysilicon layer to expose selected surface areas of the gate oxide layer; (4) performing an ion-implantation process through the exposed areas of the gate oxide layer so as to form a plurality of source/drain regions in the substrate, the source/drain regions serving as a plurality of bit lines for the ROM device; (5) removing selected portions of the remaining portions of the first polysilicon layer so as to an array of major gate structures on the substrate; (6) forming a plurality of sidewall spacers respectively on the sidewalls of the plurality of major gate structures; (7) forming a plurality of second polysilicon layers respectively between each neighboring pair of the major gate structures to serve as a plurality of minor gate structures; the plurality of major gate structures and the minor gate structure therebetween in combination being associated with a plurality of memory cells for the ROM device, with each memory cell including one major gate structure and one neighboring minor gate structure; (8) forming a dielectric layer over the memory cells; (9) from the memory cells of the ROM device, locating a first selected group of the memory cells that are to be set to a first logic state, a second selected group of the memory cells that are to be set to a second logic state, a third selected group of the memory cells that are to be set to a third logic state, and a fourth selected group of the memory cells that are to be set to a fourth logic state; then performing a mask-programming process so as to form a plurality of contact windows in the dielectric layer in such a manner that the contact windows expose all of the major gate structures that are associated with the first selected group of the memory cells, all of the minor gate structures that are associated with the second selected group of the memory cells, and all of the sidewall spaces and part of the abutting major and minor gate structures that are associated with the third group of memory cells, with all of the major and minor gate structures that are associated with the fourth selected group of the memory cells being isolated by the dielectric layer; (10) forming a conductive layer over the dielectric layer, the conductive layer filling up all of the contact windows in the dielectric layer; and (11) removing selected portions of the conductive layer so as to form a plurality of substantially parallel-spaced word lines.