US5812416A
Expired / Lapsed
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Integrated circuit design decomposition
Assignee: Bell Semiconductor LLC
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Filing: 1996-07-18
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Granted: 1998-09-22
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Expires: 2016-07-18
Abstract
Abstract Methods and systems of automatically generating synthesis scripts and hierarchical flow/connectivity diagrams are provided. The user inputs design constraints, clock characteristics, technology files, and HDL code. The system handles cores, megafunctions, hardmacs, and black boxes appropriately for synthesis. During synthesis, individual modules in the HDL code may change. The system manages these incremental changes by generating incremental scripts which 1) compile, map and model the modules that have been changed and 2) characterize, compile and model the modules that have been changed in the hierarchy under that instance. During the iterative design process, new hierarchical flow diagrams may be generated to understand the full effect of the incremental changes.
Inventors
- 👤 Vilas V. Gupte
- 👤 Sanjay Adkar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:48
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
101 words
In a computer, a method of generating a gate level specification of an integrated circuit, comprising the steps of: receiving as input user-specified constraints and a programming language description of the integrated circuit; generating at least one synthesis script for the integrated circuit that specifies the following steps: (i) synthesizing lower level modules according to default constraints; (ii) synthesizing a top level module according to the user-specified constraints; and (iii) thereafter characterizing the synthesized lower level modules according to the user-specified constraints; and generating the gate level specification of the integrated circuit with the at least one synthesis script as input.
Claim 2
Dependent Claim
101 words
In a computer, a method of generating a gate level specification of an integrated circuit, comprising the steps of: receiving as input user-specified constraints and a programming language description of the integrated circuit; generating at least one synthesis script for the integrated circuit that specifies the following steps: (i) synthesizing lower level modules according to default constraints; (ii) synthesizing a top level module according to the user-specified constraints; and (iii) thereafter characterizing the synthesized lower level modules according to the user-specified constraints; and generating the gate level specification of the integrated circuit with the at least one synthesis script as input.
Claim 3
Dependent Claim
32 words
The method of claim 1, further comprising the step of receiving input that changes a hierarchy of the programming language description of the integrated circuit in the at least one synthesis script.
Claim 4
Dependent Claim
27 words
The method of claim 1, wherein the at least one synthesis script specifies that a plurality of processes generate the gate level specification of the integrated circuit.
Claim 5
Dependent Claim
23 words
The method of claim 1, further comprising the step of receiving a design specific synthesis recipe for changing hierarchy of the integrated circuit.
Claim 6
Dependent Claim
38 words
The method of claim 1, further comprising the step of receiving a design specific synthesis recipe specifying areas of the integrated circuit that should not be altered during generation of the gate level specification of the integrated circuit.
Claim 7
Dependent Claim
40 words
The method of claim 1, wherein at least two synthesis scripts are generated and executed on different processors including the following steps: parallelizing execution of synthesis scripts according to hierarchy level; and merging parallel synthesis scripts into another hierarchy level.
Claim 8
Dependent Claim
23 words
The method of claim 6, further comprising the step of merging parallel synthesis scripts into another level until the top level is reached.
Claim 9
Dependent Claim
14 words
The method of claim 1, further comprising the step of generating a timing representation.
Claim 10
Dependent Claim
16 words
The method of claim 1, wherein the user-specified characteristics include design constraints, clock characteristics, technology information.
Claim 11
Dependent Claim
96 words
A computer comprising: means for receiving as input user-specified constraints and a programming language description of an integrated circuit; means for generating at least one synthesis script for the integrated circuit that specifies the following: (i) means for synthesizing lower level modules according to default constraints; (ii) means for synthesizing a top level module according to the user-specified constraints; and (iii) means for thereafter characterizing the synthesized lower level modules according to the user-specified constraints; and means for generating a gate level specification of the integrated circuit with the at least one synthesis script as input.
Claim 12
Dependent Claim
96 words
A computer comprising: means for receiving as input user-specified constraints and a programming language description of an integrated circuit; means for generating at least one synthesis script for the integrated circuit that specifies the following: (i) means for synthesizing lower level modules according to default constraints; (ii) means for synthesizing a top level module according to the user-specified constraints; and (iii) means for thereafter characterizing the synthesized lower level modules according to the user-specified constraints; and means for generating a gate level specification of the integrated circuit with the at least one synthesis script as input.
Claim 13
Dependent Claim
106 words
A computer program product that generates at least one synthesis script for an integrated circuit, comprising: code that receives as input user-specified constraints and a programming language description of the integrated circuit; code that generates the at least one synthesis script for the integrated circuit; code that generates the at least one synthesis script for the integrated circuit that specifies the following steps: (i) synthesizing lower level modules according to default constraints; (ii) synthesizing a top level module according to the user-specified constraints; and (iii) thereafter characterizing the synthesized lower level modules according to the user-specified constraints; and a computer readable medium that stores the codes.
Claim 14
Dependent Claim
106 words
A computer program product that generates at least one synthesis script for an integrated circuit, comprising: code that receives as input user-specified constraints and a programming language description of the integrated circuit; code that generates the at least one synthesis script for the integrated circuit; code that generates the at least one synthesis script for the integrated circuit that specifies the following steps: (i) synthesizing lower level modules according to default constraints; (ii) synthesizing a top level module according to the user-specified constraints; and (iii) thereafter characterizing the synthesized lower level modules according to the user-specified constraints; and a computer readable medium that stores the codes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |