US5812449A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same
Assignee: SK Hynix Inc
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Filing: 1996-05-10
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Granted: 1998-09-22
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Expires: 2016-05-10
Abstract
Abstract The present invention relates to a flash EEPROM cell, method of manufacturing the same, and method of programming and reading the same and, more particularly, to a flash EEPROM cell constructed in such a way that two floating gates are formed on top of a channel region to implement a memory cell to, and from, which 4-numeration information can be programmed and read out, and an output of 4-numeration information is obtained depending on the programming or erasing of each of the two floating gates.
Inventors
- 👤 Bok Nam Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:09
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/0408; G11C16/0441; G11C16/0458; G11C16/06; G11C16/10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10D64/00; H10D64/01; H10D64/031; H10D64/035; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5612
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
260 words
A method of programming a flash EEPROM cell having first and second floating gates horizontally adjacent to each other and electrically separated from a silicon substrate by a tunnel oxide film, a dielectric film formed over said first and second floating gates, a control gate formed on said dielectric film; source and drain regions formed in said silicon substrate, and regions being partially overlapped with said first and second floating gates, respectively, said method comprising the steps of: applying bias voltage to said control gate and said source and drain regions so that hot electrons are infected into said first and second floating gates; selectively discharging said hot electrons infected into said first and second floating gates depending on a condition of the bias voltage applied to said control gate and said source and drain regions, so that 4 numeration information is programmed into said flash EEPROM cell, by: using said bias voltage which is higher than that applied to said drain and a ground potential is applied to said source to inject hot electrons into said first and second floating gates; applying a ground potential to said control gate to discharge the hot electrons into said second floating gate and floating said source region and applying said drain region with higher voltage than that applied to said control gate; and applying a ground potential to said control gate to discharge the hot electrons injected into said first and second floating gates and applying a voltage higher than that applied to said control gate to said source and drain regions.
Claim 2
Independent Claim
260 words
A method of programming a flash EEPROM cell having first and second floating gates horizontally adjacent to each other and electrically separated from a silicon substrate by a tunnel oxide film, a dielectric film formed over said first and second floating gates, a control gate formed on said dielectric film; source and drain regions formed in said silicon substrate, and regions being partially overlapped with said first and second floating gates, respectively, said method comprising the steps of: applying bias voltage to said control gate and said source and drain regions so that hot electrons are infected into said first and second floating gates; selectively discharging said hot electrons infected into said first and second floating gates depending on a condition of the bias voltage applied to said control gate and said source and drain regions, so that 4 numeration information is programmed into said flash EEPROM cell, by: using said bias voltage which is higher than that applied to said drain and a ground potential is applied to said source to inject hot electrons into said first and second floating gates; applying a ground potential to said control gate to discharge the hot electrons into said second floating gate and floating said source region and applying said drain region with higher voltage than that applied to said control gate; and applying a ground potential to said control gate to discharge the hot electrons injected into said first and second floating gates and applying a voltage higher than that applied to said control gate to said source and drain regions.
Claim 3
Independent Claim
231 words
A method of reading a flash EEPROM cell having first and second floating gates horizontally adjacent to each other and electrically separated from a silicon substrate by a tunnel oxide film, a dielectric film formed over said first and second floating gates, a control gate formed on said dielectric film, a source and drain regions formed in said silicon substrate, said regions being partially overlapped with said first and second floating gates respectively, said method comprising the steps of: applying a forward bias voltage between said source and drain regions with a constant voltage being applied to said control gate; applying a reverse bias voltage between said source and drain regions under a constant voltage applied to said control gate; applying a reverse bias voltage between said source and drain regions under a constant voltage applied to said control gate; reading out 4 numeration formation programmed by hot electrons injected selectively into said first and second floating gates depending upon existence of drain and source current; at the time of applying forward bias voltage, said source region is applied with the ground potential, applying a higher voltage than that applied to said drain region to said control gate; and at a time of applying reverse bias voltage, applying the ground potential to said drain region and applying a higher voltage than that applied to said source region to said control gate.
Claim 4
Independent Claim
231 words
A method of reading a flash EEPROM cell having first and second floating gates horizontally adjacent to each other and electrically separated from a silicon substrate by a tunnel oxide film, a dielectric film formed over said first and second floating gates, a control gate formed on said dielectric film, a source and drain regions formed in said silicon substrate, said regions being partially overlapped with said first and second floating gates respectively, said method comprising the steps of: applying a forward bias voltage between said source and drain regions with a constant voltage being applied to said control gate; applying a reverse bias voltage between said source and drain regions under a constant voltage applied to said control gate; applying a reverse bias voltage between said source and drain regions under a constant voltage applied to said control gate; reading out 4 numeration formation programmed by hot electrons injected selectively into said first and second floating gates depending upon existence of drain and source current; at the time of applying forward bias voltage, said source region is applied with the ground potential, applying a higher voltage than that applied to said drain region to said control gate; and at a time of applying reverse bias voltage, applying the ground potential to said drain region and applying a higher voltage than that applied to said source region to said control gate.
References Cited (Backward Citations)
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