US5812469A
Expired / Lapsed
US
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Method and apparatus for testing multi-port memory
Assignee: LogicVision Inc
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Filing: 1996-12-31
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Granted: 1998-09-22
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Expires: 2016-12-31
Abstract
Abstract A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
Inventors
- 👤 Benoit Nadeau-Dostie
- 👤 Jean-Francois Cote
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:43
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G11C29/28; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
81 words
Apparatus for testing a multi-port memory having a plurality of memory cells and a first port and a second port, said apparatus comprising: means for applying testing to a first memory cell of the multiport memory via the first port; and means for concurrently reading from a second memory cell of the multiport memory via the second port while writing to the first memory cell; and means for comparing a value read from the second memory cell to an expected value.
Claim 2
Dependent Claim
81 words
Apparatus for testing a multi-port memory having a plurality of memory cells and a first port and a second port, said apparatus comprising: means for applying testing to a first memory cell of the multiport memory via the first port; and means for concurrently reading from a second memory cell of the multiport memory via the second port while writing to the first memory cell; and means for comparing a value read from the second memory cell to an expected value.
Claim 3
Dependent Claim
63 words
Apparatus as claimed in claim 1 wherein the memory includes a plurality of rows and a plurality of columns and each row and column intersect at a memory cell and wherein said means for applying testing includes means for applying testing to one memory cell and said means for reading via the second port includes means for reading from an adjacent memory cell.
Claim 4
Dependent Claim
75 words
Apparatus as claimed in claim 2 wherein the memory includes n rows and m columns, where m and n are positive integers, and wherein each memory cell is designated as cell(i,j) where i=1,2, . . . ,n-1,n and j=1,2, . . . ,m-1,m, wherein said means for applying read/write testing includes means for applying read/write testing to a cell(i,j) and said means for reading via the second port includes means for reading from a cell(i+1,j).
Claim 5
Independent Claim
76 words
A method of testing a multi-port memory having a plurality of memory cells and a first port and a second port, said method comprising applying testing to a first memory cell of the multiport memory via the first port; and concurrently reading from a second memory cell of the multiport memory via the second port while writing to the first memory cell; and comparing a value read from the second memory cell to an expected value.
Claim 6
Independent Claim
76 words
A method of testing a multi-port memory having a plurality of memory cells and a first port and a second port, said method comprising applying testing to a first memory cell of the multiport memory via the first port; and concurrently reading from a second memory cell of the multiport memory via the second port while writing to the first memory cell; and comparing a value read from the second memory cell to an expected value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |