US5815438A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Optimized biasing scheme for NAND read and hot-carrier write operations
Assignee: VALLEY DEVICE MANAGEMENT
•
Filing: 1997-02-28
•
Granted: 1998-09-29
•
Expires: 2017-02-28
Abstract
Abstract There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the floating gate device during the read operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.
Inventors
- 👤 Sameer S. Haddad
- 👤 Pau-Ling Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:37
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427; G11C16/26
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
89 words
A method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate, said method comprising the steps of: applying a first positive pulse voltage having a ramp-rate characteristic on its leading edge to the drain of the floating gate device during the read operation; and simultaneously applying a second positive pulse voltage to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.
Claim 2
Independent Claim
89 words
A method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate, said method comprising the steps of: applying a first positive pulse voltage having a ramp-rate characteristic on its leading edge to the drain of the floating gate device during the read operation; and simultaneously applying a second positive pulse voltage to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.
Claim 3
Dependent Claim
26 words
A method as claimed in claim 1, wherein said second positive pulse voltage has a magnitude higher than the magnitude of said first positive pulse voltage.
Claim 4
Dependent Claim
22 words
A method as claimed in claim 2, wherein said first positive pulse voltage has a magnitude between +2.5 volts to +3.5 volts.
Claim 5
Dependent Claim
22 words
A method as claimed in claim 3, wherein said second positive pulse voltage has a magnitude between +3.3 volts to +5.0 volts.
Claim 6
Dependent Claim
22 words
A method as claimed in claim 4, wherein said first positive pulse voltage has a width in the range of 5-10 μS.
Claim 7
Dependent Claim
19 words
A method as claimed in claim 5, wherein said first positive pulse voltage has a width of 10 μS.
Claim 8
Dependent Claim
46 words
A method as claimed in claim 6, wherein the ramp-rate characteristic on the leading edge of said first positive pulse voltage has an initial magnitude of 0 volts and gradually increases to the magnitude of +3.5 volts in a time period of greater than 100 nS.
Claim 9
Dependent Claim
14 words
A method as claimed in claim 7, wherein the time period is 1 μS.
Claim 10
Dependent Claim
31 words
A method as claimed in claim 1, wherein said ramp-rate characteristic is sufficiently slow so as to permit the source voltage on the floating gate device to follow the drain voltage.
Claim 11
Independent Claim
119 words
A method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate, said method comprising the steps of: applying a first positive pulse voltage having a ramp-rate characteristic on its leading edge to the drain of the floating gate device during the read operation; simultaneously applying a second positive pulse voltage to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage; and applying said first positive pulse voltage with an initial magnitude of 0 volts and gradually increasing the magnitude to +3.5 volts in a time period of 1 μS or larger.
Claim 12
Independent Claim
119 words
A method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate, said method comprising the steps of: applying a first positive pulse voltage having a ramp-rate characteristic on its leading edge to the drain of the floating gate device during the read operation; simultaneously applying a second positive pulse voltage to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage; and applying said first positive pulse voltage with an initial magnitude of 0 volts and gradually increasing the magnitude to +3.5 volts in a time period of 1 μS or larger.
Claim 13
Dependent Claim
26 words
A method as claimed in claim 10, wherein said second positive pulse voltage has a magnitude higher than the magnitude of said first positive pulse voltage.
Claim 14
Dependent Claim
19 words
A method as claimed in claim 11, wherein said second positive pulse voltage has a magnitude of +5.0 volts.
Claim 15
Dependent Claim
22 words
A method as claimed in claim 12, wherein said first positive pulse voltage has a width in the range of 5-10 μS.
Claim 16
Dependent Claim
19 words
A method as claimed in claim 13, wherein said first positive pulse voltage has a width of 10 μS.
Claim 17
Independent Claim
89 words
A method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a single gate device is used as a select gate, said method comprising the steps of: applying a first positive pulse voltage having a ramp-rate characteristic on its leading edge to the drain of the single gate device during the read operation; and simultaneously applying a second positive pulse voltage to the control gate of the single gate device during the read operation so as to overlap the first positive pulse voltage.
Claim 18
Independent Claim
89 words
A method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a single gate device is used as a select gate, said method comprising the steps of: applying a first positive pulse voltage having a ramp-rate characteristic on its leading edge to the drain of the single gate device during the read operation; and simultaneously applying a second positive pulse voltage to the control gate of the single gate device during the read operation so as to overlap the first positive pulse voltage.
Claim 19
Dependent Claim
26 words
A method as claimed in claim 15, wherein said second positive pulse voltage has a magnitude higher than the magnitude of said first positive pulse voltage.
Claim 20
Dependent Claim
22 words
A method as claimed in claim 16, wherein said first positive pulse voltage has a magnitude between +2.5 volts to +3.5 volts.
Claim 21
Dependent Claim
22 words
A method as claimed in claim 17, wherein said second positive pulse voltage has a magnitude between +3.3 volts to +5.0 volts.
Claim 22
Dependent Claim
22 words
A method as claimed in claim 18, wherein said first positive pulse voltage has a width in the range of 5-10 μS.
Claim 23
Dependent Claim
19 words
A method as claimed in claim 19. wherein said first positive pulse voltage has a width of 10 μS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |