US5818751A
Expired / Lapsed
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Single-port SRAM with no read/write collisions
Assignee: Industrial Technology Research Institute
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Filing: 1997-09-08
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Granted: 1998-10-06
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Expires: 2017-09-08
Abstract
Abstract A single-port SRAM with no read/write collisions. The present invention uses some X-axis and Y-axis control circuits to reduce the amounts of lines used in the structure of the present invention, but still maintains circuitry stability.
Inventors
- 👤 Yung-Yuan Ho
- 👤 Nang-Ping Tu
- 👤 Jian-Yau Yih
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
288 words
A single-port SRAM with no read/write collisions, comprising: a plurality of memory cells, distributed in a memory cell array, each having independent data read/write paths, a read/write sequence of said memory cell controlled by a reading clock signal and a writing clock signal; a plurality of word-lines, receiving a word-line control signal for enabling and reading from or writing to a specific memory cell; a plurality of bit-lines, receiving a bit-line control signal for enabling and reading from or writing to a specific memory cell; a plurality of Y-axis control circuits, respectively coupled to each word-line, each receiving a reading word signal, a writing word signal, said reading clock signal, and said writing clock signal to output said word-line control signal, wherein said word-line control signal enables a specific memory cell on a related word-line of said Y-axis control circuit for data reading during a first half period of said reading clock signal; and said word-line control signal enables a specific memory cell on a related word-line of said Y-axis control circuit for data writing during a second half period of said reading clock signal; and a plurality of X-axis control circuits, coupled to said bit-line, each receiving a reading bit-line signal, a writing bit-line signal, said reading clock signal, said writing clock signal, and a separation clock to output said bit-line control signal, wherein said bit-line control signal enables a specific memory cell on a related bit-line of said X-axis control circuit for data reading during a first half period of said reading clock signal; and said bit-line control signal enables a specific memory cell on a related bit-line of said X-axis control circuit for data writing during a second half period of said reading clock signal.
Claim 2
Dependent Claim
288 words
A single-port SRAM with no read/write collisions, comprising: a plurality of memory cells, distributed in a memory cell array, each having independent data read/write paths, a read/write sequence of said memory cell controlled by a reading clock signal and a writing clock signal; a plurality of word-lines, receiving a word-line control signal for enabling and reading from or writing to a specific memory cell; a plurality of bit-lines, receiving a bit-line control signal for enabling and reading from or writing to a specific memory cell; a plurality of Y-axis control circuits, respectively coupled to each word-line, each receiving a reading word signal, a writing word signal, said reading clock signal, and said writing clock signal to output said word-line control signal, wherein said word-line control signal enables a specific memory cell on a related word-line of said Y-axis control circuit for data reading during a first half period of said reading clock signal; and said word-line control signal enables a specific memory cell on a related word-line of said Y-axis control circuit for data writing during a second half period of said reading clock signal; and a plurality of X-axis control circuits, coupled to said bit-line, each receiving a reading bit-line signal, a writing bit-line signal, said reading clock signal, said writing clock signal, and a separation clock to output said bit-line control signal, wherein said bit-line control signal enables a specific memory cell on a related bit-line of said X-axis control circuit for data reading during a first half period of said reading clock signal; and said bit-line control signal enables a specific memory cell on a related bit-line of said X-axis control circuit for data writing during a second half period of said reading clock signal.
Claim 3
Dependent Claim
90 words
The single-port SRAM of claim 1, wherein said Y-axis control circuit comprises: a first Y-axis AND gate, receiving said reading clock signal, and said reading word-line signal to output a word read enabling signal; a second Y-axis AND gate, receiving a signal inverted from said writing clock signal, a signal inverted from said reading clock signal, and said word writing signal to output an word write enabling signal; and a Y-axis OR gate, receiving said word read enabling signal and said word write enabling signal to output said word-line signal.
Claim 4
Dependent Claim
98 words
The single-port SRAM of claim 1, wherein said X-axis control circuit comprises: a first X-axis AND gate, receiving said reading clock signal, and said reading bit-line signal to output a bit read enabling signal; a second X-axis AND gate, receiving a signal inverted from said writing clock signal, a signal inverted from said reading clock signal, a signal inverted from said separation clock, and said bit writing signal to output an bit write enabling signal; and an X-axis OR gate, receiving said bit read enabling signal and said bit write enabling signal to output said bit-line control signal.
Claim 5
Dependent Claim
35 words
The single-port SRAM of claim 1, wherein said separation clock, whose period is half the period of said reading clock signal, limits said bit-line control signal for enabling a specific memory cell for data writing.
Claim 6
Dependent Claim
20 words
The single-port SRAM of claim 1, wherein said reading clock signal has the same period as said writing clock signal.
Claim 7
Dependent Claim
20 words
The single-port SRAM of claim 1, wherein said reading clock signal has a different period from said writing clock signal.
Claim 8
Dependent Claim
24 words
The single-port SRAM of claim 1, wherein the period of said reading clock signal is several integral multiples of said writing clock signal period.
Claim 9
Dependent Claim
24 words
The single-port SRAM of claim 1, wherein the period of said writing clock signal is several integral multiples of said reading clock signal period.
References Cited (Backward Citations)
US5675548A
Cited
US5272678A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |