US5822768A
Expired / Lapsed
US
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Dual ported memory for a unified memory architecture
Assignee: OPTi Inc
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Filing: 1996-01-11
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Granted: 1998-10-13
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Expires: 2016-01-11
Abstract
Abstract A unified memory architecture includes a dual ported memory, core logic and a serial controller. The dual ported memory contains a random access port and a serial port to support concurrent accesses, after an initial serial port set-up time, through the serial port and the random access port. The core logic handles accesses to the random access port on the dual ported memory for all devices except the serial controller. The serial controller also accesses the dual ported memory through the random access port, and it also receives serial data, for use in a serial data operation, through the serial port. The serial controller generates a serial port load command through the random access port to effectuate the serial data transfer. The serial controller may be a graphics controller that utilizes the dual ported memory as a frame buffer. For this embodiment, the graphics controller executes screen refresh operations through use of the serial port. A serial port load command is defined for both a synchronous and an asynchronous interface for the dual ported memory.
Inventors
- 👤 Rajesh Shakkarwar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G2360/00; G09G2360/12; G09G2360/125; G09G2360/126; G09G5/001; G09G5/363
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
232 words
A unified memory architecture comprising: a memory comprising a plurality of memory cells, for shared use as both general purpose memory and serial controller memory, and comprising a random access port and a serial port, said random access port for receiving random access memory cycles and serial port load cycles, wherein said serial port load cycles specify selected memory cells in a serial controller memory area to read from said serial port; core logic for accessing, in response to memory access requests to a general purpose memory area, said memory through said random access port and through generation of random access memory cycles; a serial controller coupled to said memory for generating serial port load commands during serial port load cycles to specify a first selected group of said memory cells in said serial controller memory area, and for reading data from said first selected group of said memory cells through said serial port; and wherein said core logic and said serial controller arbitrate for use of said random access port to effectuate random access cycles and serial port load cycles, respectively, and wherein said memory permits concurrent reading through said serial port of said first selected group of memory cells in said serial controller memory area, and access, via said random access port, to memory cells in said general purpose memory area subsequent to execution of a serial port load cycle.
Claim 2
Dependent Claim
232 words
A unified memory architecture comprising: a memory comprising a plurality of memory cells, for shared use as both general purpose memory and serial controller memory, and comprising a random access port and a serial port, said random access port for receiving random access memory cycles and serial port load cycles, wherein said serial port load cycles specify selected memory cells in a serial controller memory area to read from said serial port; core logic for accessing, in response to memory access requests to a general purpose memory area, said memory through said random access port and through generation of random access memory cycles; a serial controller coupled to said memory for generating serial port load commands during serial port load cycles to specify a first selected group of said memory cells in said serial controller memory area, and for reading data from said first selected group of said memory cells through said serial port; and wherein said core logic and said serial controller arbitrate for use of said random access port to effectuate random access cycles and serial port load cycles, respectively, and wherein said memory permits concurrent reading through said serial port of said first selected group of memory cells in said serial controller memory area, and access, via said random access port, to memory cells in said general purpose memory area subsequent to execution of a serial port load cycle.
Claim 3
Dependent Claim
83 words
The unified memory architecture as set forth in claim 1, wherein said memory comprises: control and address inputs on said random access port for receiving control and address signals; a dual port controller coupled to said control and address inputs on said random access port for receiving a serial port load command including address information to specify said selected group of said memory cells, said dual port controller for transferring data from said selected group of said memory cells to said serial port.
Claim 4
Dependent Claim
35 words
The unified memory architecture as set forth in claim 1, wherein said serial controller comprises a graphics controller for generating a serial port load command to effectuate data transfer to execute a screen refresh operation.
Claim 5
Dependent Claim
28 words
The unified memory architecture as set forth in claim 1, further comprising at least one central processing unit (CPU) coupled to said core logic for accessing said memory.
Claim 6
Dependent Claim
24 words
The unified memory architecture as set forth in claim 1, further comprising a peripheral bus coupled to said core logic and said serial controller.
Claim 7
Dependent Claim
22 words
The unified memory architecture as set forth in claim 5, wherein said peripheral bus comprising a peripher al component interconnect (PCI) bus.
Claim 8
Dependent Claim
26 words
The unified memory architecture as set forth in claim 5, further comprising at least one peripheral device coupled to said core logic for accessing said memory.
Claim 9
Dependent Claim
101 words
The unified memory architecture as set forth in claim 2, where in: said random access port comprises an asynchronous interface; said control signals comprise a row address strobe bar (RAS#), a column address strobe bar (CAS#), and a write enable bar (WE#); and said serial controller for transitioning said CAS# signal from a high logic level to an active low logic level, for generating a low logic level for said WE# signal during said active CAS#, and thereafter for transitioning said RAS# signal from a high logic level to an active low logic level to generate said serial load port command.
Claim 10
Dependent Claim
55 words
The unified memory architecture as set forth in claim 8, wherein said address information comprises a row address for selecting a row of said memory cells, said serial controller for generating said row address on said address inputs of said memory such that said row address is valid upon transitioning of said active RAS# signal.
Claim 11
Dependent Claim
74 words
The unified memory architecture as set forth in claim 9, wherein said address information further comprises a start address to identify at least one memory cell within said row of memory cells identified by said row address, said serial controller for transitioning said CAS# signal from a high logic level to an active low logic level in a subsequent cycle, and for generating a valid start address upon transitioning of said active CAS# signal.
Claim 12
Dependent Claim
22 words
The unified memory architecture as set forth in claim 1, wherein said memory c ells comprise dynamic random access memory (DRAM) cells.
Claim 13
Dependent Claim
90 words
The unified memory architecture as set forth in claim 2, wherein said control signals comprise a row address strobe bar (RAS#), a column address strobe bar (CAS#), and a write enable bar (WE#), said core logic for generating a DRAM refresh cycle to transition said CAS# signal from a high logic level to an active low logic level, for generating a high logic level for said WE# signal for said active CAS#, and thereafter for transitioning said RAS# signal from a high logic level to an active low logic level.
Claim 14
Dependent Claim
95 words
The unified memory architecture as set forth in claim 2, wherein: said random access port comprises a synchronous interface including a first clock signal; said control signals comprise a chip select bar (CS#), a write enable bar (WE#), a row address strobe bar (RAS#), a column address strobe bar (CAS#), and a clock enable (CKE); and said serial controller for driving, during a rising edge of said first clock signal, said CS# and said WE# signals to a low logic level and said CAS#, said RAS#, and said CKE signals to a high logic level.
Claim 15
Dependent Claim
47 words
The unified memory architecture as set forth in claim 13, wherein said address information comprises a bank identification for specifying a bank of said memory cells, said serial controller for generating said bank identification on said address inputs during said rising edge of said first clock signal.
Claim 16
Dependent Claim
47 words
The unified memory architecture as set forth in claim 14, wherein said address information further comprises a start address to identify a starting memory cell within said bank identified, said serial controller for generating a valid start address on said rising edge of said first clock signal.
Claim 17
Dependent Claim
217 words
A memory device for use in a unified memory architecture comprising: a plurality of memory cells comprising a general purpose memory area and a serial controller memory area; at least one serial port coupled to said memory cells for providing data from a first selected group of said memory cells in said serial controller memory area; at least one random access port coupled to said memory cells for accessing selected memory cells in said general purpose memory, said random access port for receiving random access memory cycles and serial port load cycles, wherein said serial port load cycles specify selected memory cells in said serial controller memory area to read from said serial port; and a dual port controller coupled to said random access port for receiving a serial port load command that specifies said first selected group of said memory cells in said serial controller memory area, said dual port controller for transferring data from said first selected group of said memory cells to said serial port, wherein said memory permits concurrent reading through said serial port of said first selected group of memory cells in said serial controller memory area, and access, via said random access port, to memory cells in said general purpose memory area subsequent to execution of a serial port load cycle.
Claim 18
Dependent Claim
217 words
A memory device for use in a unified memory architecture comprising: a plurality of memory cells comprising a general purpose memory area and a serial controller memory area; at least one serial port coupled to said memory cells for providing data from a first selected group of said memory cells in said serial controller memory area; at least one random access port coupled to said memory cells for accessing selected memory cells in said general purpose memory, said random access port for receiving random access memory cycles and serial port load cycles, wherein said serial port load cycles specify selected memory cells in said serial controller memory area to read from said serial port; and a dual port controller coupled to said random access port for receiving a serial port load command that specifies said first selected group of said memory cells in said serial controller memory area, said dual port controller for transferring data from said first selected group of said memory cells to said serial port, wherein said memory permits concurrent reading through said serial port of said first selected group of memory cells in said serial controller memory area, and access, via said random access port, to memory cells in said general purpose memory area subsequent to execution of a serial port load cycle.
Claim 19
Dependent Claim
103 words
The memory device as set forth in claim 16, wherein said random access port comprises an asynchronous interface including control and address inputs for receiving control and address signals, and said control signals comprise a row address strobe bar (RAS#), a column address strobe bar (CAS#), and a write enable bar (WE#), said serial port load command being defined by: said CAS# signal transitioning from a high logic level to an active low logic level; said WE# signal being a low logic level for said active CAS#; said RAS# signal thereafter transitioning from a high low level to an active low logic level.
Claim 20
Dependent Claim
46 words
The memory device as set forth in claim 17, wherein said address information comprises a row address for selecting a row in said memory, said row address being received on said address inputs, and said row address being valid upon transitioning of said active RAS# signal.
Claim 21
Dependent Claim
77 words
The memory device as set forth in claim 18, wherein said address information further comprises a start address to identify at least one memory cell within said row of memory cells identified by said row address, said serial port load command further being defined by: said CAS# signal transitioning from a high logic level to an active low logic level in a subsequent cycle; and said start address being valid upon transitioning of said active CAS# signal.
Claim 22
Dependent Claim
19 words
The memory as set forth in claim 16, wherein said memory cells comprise dynamic random access memory (DRAM) cells.
Claim 23
Dependent Claim
83 words
The memory as set forth in claim 20, wherein said control signals comprise a row address strobe bar (RAS#), a column address strobe bar (CAS#), and a write enable bar (WE#), wherein a DRAM refresh cycle is defined by: said CAS# signal transitioning from a high logic level to an active low logic level; said WE# signal being a high logic level for said active CAS#; and said RAS# signal thereafter transitioning from a high logic level to an active low logic level.
Claim 24
Dependent Claim
105 words
The memory device as set forth in claim 16, wherein: said random access port comprises a synchronous interface including a first clock signal; said control signals comprise a chip select bar (CS#), a write enable bar (WE#), a row address strobe bar (RAS#), a column address strobe bar (CAS#), and a clock enable (CKE), said serial port load command being defined by: said CS# and said WE# signals being a low logic level during a rising edge of said first clock signal; and said CAS#, said RAS# and said CKE signals being a high logic level during said rising edge of said first clock signal.
Claim 25
Dependent Claim
52 words
The memory device as set forth in claim 22, wherein said address information comprises a bank identification for specifying a bank of said memory cells, said serial port load command further being defined by said bank identification being valid on said address inputs during said rising edge of said first clock signal.
Claim 26
Dependent Claim
50 words
The memory device as set forth in claim 23, wherein said address information further comprises a start address to identify a starting memory cell within said bank identified, said serial port load command further being defined by a valid start address on said rising edge of said first clock signal.
Claim 27
Independent Claim
181 words
A method for utilizing a single memory comprising a general purpose memory area and a serial controller memory area in a unified memory architecture, said method comprising the steps of: accessing said general purpose memory area in said single memory, in response to memory requests, from a random access port of said single memory during random access memory cycles; transmitting from a serial controller to said random access port, during serial port load cycles, a serial port load command to set-up transfer of a first group of selected memory cells in said serial controller memory area of said single memory; and transmitting from said serial port on said memory data from said first group of selected memory cells in said serial controller memory area to said serial controller, wherein said memory permits concurrent reading through said serial port of said first selected group of memory cells in said serial controller memory area, and access, via said random access port, to a group of said memory cells in said general purpose memory area subsequent to execution of a serial port load cycle.
Claim 28
Independent Claim
181 words
A method for utilizing a single memory comprising a general purpose memory area and a serial controller memory area in a unified memory architecture, said method comprising the steps of: accessing said general purpose memory area in said single memory, in response to memory requests, from a random access port of said single memory during random access memory cycles; transmitting from a serial controller to said random access port, during serial port load cycles, a serial port load command to set-up transfer of a first group of selected memory cells in said serial controller memory area of said single memory; and transmitting from said serial port on said memory data from said first group of selected memory cells in said serial controller memory area to said serial controller, wherein said memory permits concurrent reading through said serial port of said first selected group of memory cells in said serial controller memory area, and access, via said random access port, to a group of said memory cells in said general purpose memory area subsequent to execution of a serial port load cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |