Charge pump

Claim 2

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a primary surface; a well region of a second conductivity type in said semiconductor substrate at said primary surface; a first doped region of said first conductivity in said well region; a second doped region of said first conductivity type in said well region, said second doped region spaced from and electrically connected to said first doped region; an insulation layer on said primary surface of said substrate overlying respective portions of said first and second doped regions and a portion of said well region between said first and second doped regions; a gate electrode on said insulation layer over said respective portions of said first and second doped regions and at least a part of said portion of said well region between said first and second doped regions; and a conductive layer electrically shorting at least one of said first and second doped regions to said well region.

Claim 3

A semiconductor device in accordance with claim 1, wherein said first conductivity type is p conductivity type and said second conductivity type is n conductivity type.

Claim 4

A semiconductor device in accordance with claim 1, wherein said first and second doped regions constitute a first capacitor electrode of an MIS capacitor, said insulator constitutes a dielectric portion of said MIS capacitor, and said gate electrode constitutes a second capacitor electrode of said MIS capacitor.

Claim 5

A semiconductor integrated circuit comprising: a semiconductor substrate; a well region of a first conductivity type in said substrate; a transistor including: a source region of a second conductivity type in said well region; a drain region of a second conductivity type in said well region spaced from said source region; and an insulated gate electrode overlying a portion of said well region between said source and drain regions, said insulated gate receiving a charge sharing signal; and a first charge sharing capacitor having a first capacitor electrode electrically connected to said well region to adjust a body effect of said transistor, and coupled to receive a voltage signal, and a second capacitor electrode connected to one of said source and drain regions; and a second charge sharing capacitor having a first capacitor electrode coupled to another one of said source and drain regions, and a second capacitor electrode.

Claim 6

A semiconductor integrated circuit comprising: a semiconductor substrate; a well region of a first conductivity type in said substrate; a transistor including: a source region of a second conductivity type in said well region; a drain region of a second conductivity type in said well region spaced from said source region; and an insulated gate electrode overlying a portion of said well region between said source and drain regions, said insulated gate receiving a charge sharing signal; and a first charge sharing capacitor having a first capacitor electrode electrically connected to said well region to adjust a body effect of said transistor, and coupled to receive a voltage signal, and a second capacitor electrode connected to one of said source and drain regions; and a second charge sharing capacitor having a first capacitor electrode coupled to another one of said source and drain regions, and a second capacitor electrode.

Claim 7

A semiconductor integrated circuit in accordance with claim 4, wherein said second capacitor electrode of said second charge sharing capacitor is coupled to receive said voltage signal, and said voltage signal is delayed by a predetermined time duration.

Claim 8

A semiconductor integrated circuit in accordance with claim 5, further comprising: a precharge transistor having a drain electrode coupled to a reference voltage, a gate electrode receiving a precharge signal, and a source electrode, said source electrode precharged to a predetermined level in response to said precharge signal; a boot capacitor having a first electrode coupled to said source electrode of said precharge transistor, and a second electrode coupled to said voltage signal; and a pass transistor having a gate electrode coupled to said other one of said source and drain regions and said second capacitor electrode of said first capacitor, a source electrode connected to said first electrode of said boot capacitor, and a drain electrode, said drain electrode supplying a potential to said semiconductor substrate corresponding to a voltage appearing at said first electrode of said boot capacitor.

Claim 9

A semiconductor integrated circuit, comprising: an phase circuit generating an alternating voltage signal; a boot capacitor having a first electrode coupled to receive said alternating voltage signal and a second electrode; a first p-channel MOS transistor having a first terminal coupled to a reference voltage, a control terminal receiving a precharge signal, and a second terminal coupled to said second electrode of said boot capacitor, said second terminal being precharged to a predetermined level in response to said precharge signal, a second p-channel transistor having a first terminal connected to said second electrode of said boot capacitor, a control terminal, and a second terminal; a biasing circuit supplying a control signal to said control terminal of said second p-channel transistor of a voltage magnitude that is greater than a voltage magnitude of said alternating voltage signal, wherein a voltage appearing at said second electrode of said boot capacitor is passed to said second terminal of said second p-channel transistor substantially without a threshold voltage drop.

Claim 10

A semiconductor integrated circuit, comprising: an phase circuit generating an alternating voltage signal; a boot capacitor having a first electrode coupled to receive said alternating voltage signal and a second electrode; a first p-channel MOS transistor having a first terminal coupled to a reference voltage, a control terminal receiving a precharge signal, and a second terminal coupled to said second electrode of said boot capacitor, said second terminal being precharged to a predetermined level in response to said precharge signal, a second p-channel transistor having a first terminal connected to said second electrode of said boot capacitor, a control terminal, and a second terminal; a biasing circuit supplying a control signal to said control terminal of said second p-channel transistor of a voltage magnitude that is greater than a voltage magnitude of said alternating voltage signal, wherein a voltage appearing at said second electrode of said boot capacitor is passed to said second terminal of said second p-channel transistor substantially without a threshold voltage drop.

Claim 11

A semiconductor integrated circuit in accordance with claim 7, further comprising a semiconductor substrate, wherein said voltage appearing at said second electrode of said boot capacitor is supplied to said semiconductor substrate.

Claim 12

A semiconductor integrated circuit in accordance with claim 7, wherein said biasing circuit comprises: a first charge-sharing capacitor having a first electrode receiving said alternating voltage and a second electrode; a switching element having a first terminal connected to said second electrode of said first charge-sharing capacitor, a gate electrode receiving a charge-sharing signal, and a second terminal; and a second charge-sharing capacitor having a first electrode coupled to receive said alternating voltage delayed by a predetermined duration, and a second electrode, said second terminal of said switching element and said second electrode of said second charge-sharing capacitor connected in common to an output node of said biasing circuit, said output node coupled to supply said control signal to said gate of said second p-channel transistor.

Claim 13

A semiconductor integrated circuit in accordance with claim 9, further comprising: a semiconductor substrate having a first conductivity type; and a well region having a second conductivity type, wherein said first and second terminals of said switching element include first and second doped regions, respectively, in said well region, and said first electrode of said first charge sharing capacitor is electrically connected to said well region.

Claim 14

A semiconductor device in accordance with claim 9, further comprising: a semiconductor substrate having a first conductivity type; and a well region having a second conductivity type, wherein said first electrode of said boot capacitor includes a region of said first conductivity type formed in and electrically connected to said well region.

Claim 15

A semiconductor device in accordance with claim 9, further comprising: a semiconductor substrate having a first conductivity type; and a well region having a second conductivity type, wherein said first electrode of said first charge-sharing capacitor includes a region of said first conductivity type formed in and electrically connected to said well region.

Claim 16

A semiconductor device in accordance with claim 9, further comprising: a semiconductor substrate having a first conductivity type; and a well region having a second conductivity type, wherein said first electrode of said second charge-sharing capacitor includes a region of said first conductivity type formed in and electrically connected to said well region.

Claim 17

A semiconductor device in accordance with claim 9, wherein said charge-sharing signal is a potential signal including said voltage appearing at said second electrode of said boot capacitor.

Claim 18

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first well region of a second conductivity type in said substrate; a second well region of said first conductivity type in said first well region; a transistor including: a first doped region of said second conductivity type in said second well region; a second doped region of said second conductivity type in said second well region spaced from said first doped region; and an insulated gate overlying a portion of said second well region between said first and second doped regions; and a capacitor formed in association with said substrate and spaced from said insulated gate, said capacitor having an electrode electrically connected to said second well region.

Claim 19

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first well region of a second conductivity type in said substrate; a second well region of said first conductivity type in said first well region; a transistor including: a first doped region of said second conductivity type in said second well region; a second doped region of said second conductivity type in said second well region spaced from said first doped region; and an insulated gate overlying a portion of said second well region between said first and second doped regions; and a capacitor formed in association with said substrate and spaced from said insulated gate, said capacitor having an electrode electrically connected to said second well region.

Claim 20

A semiconductor device in accordance with claim 15, wherein said electrode connected to said second well region is further connected to receive a signal, and said capacitor is adapted to produce a voltage on another electrode of said capacitor in response to said signal.

Claim 21

A semiconductor device in accordance with claim 16, wherein said transistor is configured to have a reduced body effect upon receipt of said signal.

Claim 22

A semiconductor device in accordance with claim 16, wherein said another electrode is coupled to said insulated gate, and said voltage is supplied to said insulated gate to render said transistor conductive.

Claim 23

A semiconductor integrated circuit comprising: a semiconductor substrate; a well region of a first conductivity type in said substrate; a transistor including: a source region of a second conductivity type in said well region; a drain region of a second conductivity type in said well region spaced from said source region; and an insulated gate electrode overlying a portion of said well region between said source and drain regions, said insulated gate receiving a charge sharing signal; a switched potential node coupled to said well region for reducing a body-effect of said transistor; and a first charge sharing capacitor coupled to one of said source and drain regions; and a second charge sharing capacitor coupled to the other of said source and drain regions.

Claim 24

A semiconductor integrated circuit comprising: a semiconductor substrate; a well region of a first conductivity type in said substrate; a transistor including: a source region of a second conductivity type in said well region; a drain region of a second conductivity type in said well region spaced from said source region; and an insulated gate electrode overlying a portion of said well region between said source and drain regions, said insulated gate receiving a charge sharing signal; a switched potential node coupled to said well region for reducing a body-effect of said transistor; and a first charge sharing capacitor coupled to one of said source and drain regions; and a second charge sharing capacitor coupled to the other of said source and drain regions.

Claim 25

A semiconductor integrated circuit in accordance with claim 19, wherein said first charge sharing capacitor has a first capacitor electrode coupled to receive a voltage signal, and a second capacitor electrode coupled to said one of said source and drain regions, and said second charge sharing capacitor has a first capacitor electrode coupled to said other one of said source and drain regions, and a second capacitor electrode coupled to receive said voltage signal, said voltage signal being delayed by a predetermined duration.

Claim 26

A semiconductor integrated circuit in accordance with claim 20, further comprising: a precharge transistor having a drain electrode coupled to a reference voltage, a gate electrode receiving a precharge signal, and a source electrode, said source electrode precharged to a predetermined level in response to said precharge signal; a boot capacitor having a first electrode coupled to said source electrode of said precharge transistor, and a second electrode coupled to said voltage signal; and a pass transistor having a gate electrode coupled to said other one of said source and drain regions and said second capacitor electrode of said first capacitor, a source electrode connected to said first electrode of said boot capacitor, and a drain electrode, said drain electrode supplying a potential to said semiconductor substrate corresponding to a voltage appearing at said first electrode of said boot capacitor.

Claim 27

A semiconductor device in accordance with claim 9, further comprising: a semiconductor substrate having a first conductivity type; and a well region having a second conductivity type, wherein said first electrode of said first charge-sharing capacitor includes a region of said first conductivity type electrically connected to said well region.