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US5832492A
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Method of scheduling interrupts to the linked lists of transfer descriptors scheduled at intervals on a serial bus
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-09-05
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Granted: 1998-11-03
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Expires: 2016-09-05
Abstract
Abstract A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.
Inventors
- 👤 David R. Wooten
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/102; G06F13/14; G06F13/20; G06F13/24; G06F13/26; Y; Y10; Y10S; Y10S707/00; Y10S707/99941; Y10S707/99942; Y10S707/99943
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
153 words
A method of scheduling interrupts, the method comprising the steps of: (a) developing a tree-structured interrupt list comprised of stages numbering x, each stage having a number of individual interrupt lists equal to 2 x-1 , two interrupt lists from each higher numbered stage linking to a single interrupt list of a next lower numbered stage to form a linked list, each interrupt list of a lower numbered stage being linked to only two interrupt lists of a higher numbered stage, each stage corresponding to a polling interval; (b) developing a table having a number of entries corresponding to the number of interrupt lists of the highest stage, each entry containing a pointer to one of the interrupt lists of the highest stage; (c) indexing into one of the table entries according to a frame number on the occurance of a frame boundary; and (d) processing the interrupts according to the linked list.
Claim 2
Independent Claim
153 words
A method of scheduling interrupts, the method comprising the steps of: (a) developing a tree-structured interrupt list comprised of stages numbering x, each stage having a number of individual interrupt lists equal to 2 x-1 , two interrupt lists from each higher numbered stage linking to a single interrupt list of a next lower numbered stage to form a linked list, each interrupt list of a lower numbered stage being linked to only two interrupt lists of a higher numbered stage, each stage corresponding to a polling interval; (b) developing a table having a number of entries corresponding to the number of interrupt lists of the highest stage, each entry containing a pointer to one of the interrupt lists of the highest stage; (c) indexing into one of the table entries according to a frame number on the occurance of a frame boundary; and (d) processing the interrupts according to the linked list.
Claim 3
Dependent Claim
31 words
The method of claim 1, further comprising the step of: (e) indicating an error condition if all the interrupts of the linked list are not processed before the frame has ended.
Claim 4
Dependent Claim
119 words
The method of claim 1, wherein each individual interrupt list is a list of endpoint descriptors with each endpoint descriptor pointing to a queue of transfer descriptors and wherein step (d) further comprises the steps of: (f) selecting a list; (g) obtaining an endpoint descriptor from the selected list; (h) obtaining a transfer descriptor from the queue of the endpoint descriptor; (i) processing the interrupt identified in the transfer descriptor; (j) determining if a next transfer descriptor is available; (k) repeating steps (h)-(j) if a next transfer descriptor is available; (l) determining if a next endpoint descriptor is available if a next transfer descriptor is not available; and (m) repeating steps (g)-(l) if a next endpoint descriptor is available.
Claim 5
Dependent Claim
93 words
A data structure in a memory arranged to define a linked list, comprising: one or more endpoint descriptors, each including: a transfer descriptor field; and a next endpoint descriptor field; and one or more transfer descriptors, each including: a next transfer descriptor field for linking to a next transfer descriptor if not null, wherein said endpoint descriptors are linked to a subsequent endpoint descriptor if said next endpoint descriptor field is not null and each said endpoint descriptor is linked to a first transfer descriptor if said transfer descriptor field is not null.
Claim 6
Dependent Claim
93 words
A data structure in a memory arranged to define a linked list, comprising: one or more endpoint descriptors, each including: a transfer descriptor field; and a next endpoint descriptor field; and one or more transfer descriptors, each including: a next transfer descriptor field for linking to a next transfer descriptor if not null, wherein said endpoint descriptors are linked to a subsequent endpoint descriptor if said next endpoint descriptor field is not null and each said endpoint descriptor is linked to a first transfer descriptor if said transfer descriptor field is not null.
Claim 7
Dependent Claim
32 words
The data structure of claim 4, wherein each said transfer descriptor further comprises: a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.
Claim 8
Dependent Claim
32 words
The data structure of claim 5, wherein each said transfer descriptor further comprises: a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.
Claim 9
Dependent Claim
38 words
The data structure of claim 4, wherein each said endpoint descriptor further includes: a tail pointer field for indicating the presence of an transfer descriptor if said tail pointer field is not equal to said transfer descriptor field.
Claim 10
Dependent Claim
122 words
A computer system, comprising: a processor; a hard disk subsystem coupled to said processor; a serial bus host controller coupled to said processor; a memory coupled to said processor and said serial bus host controller arranged to define a data structure, comprising: one or more endpoint descriptors, each including: a transfer descriptor field; and a next endpoint descriptor field; and one or more transfer descriptors, each including: a next transfer descriptor field for linking to a next transfer descriptor if not null, wherein said endpoint descriptors are linked to a subsequent endpoint descriptor if said next endpoint descriptor field is not null and each said endpoint descriptor is linked to a first transfer descriptor if said transfer descriptor field is not null.
Claim 11
Dependent Claim
122 words
A computer system, comprising: a processor; a hard disk subsystem coupled to said processor; a serial bus host controller coupled to said processor; a memory coupled to said processor and said serial bus host controller arranged to define a data structure, comprising: one or more endpoint descriptors, each including: a transfer descriptor field; and a next endpoint descriptor field; and one or more transfer descriptors, each including: a next transfer descriptor field for linking to a next transfer descriptor if not null, wherein said endpoint descriptors are linked to a subsequent endpoint descriptor if said next endpoint descriptor field is not null and each said endpoint descriptor is linked to a first transfer descriptor if said transfer descriptor field is not null.
Claim 12
Dependent Claim
32 words
The computer system of claim 8, wherein each said transfer descriptor further comprises: a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.
Claim 13
Dependent Claim
32 words
The computer system of claim 9, wherein each said transfer descriptor further comprises: a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.
Claim 14
Dependent Claim
38 words
The computer system of claim 8, wherein each said endpoint descriptor further includes: a tail pointer field for indicating the presence of an transfer descriptor if said tail pointer field is not equal to said transfer descriptor field.
References Cited (Backward Citations)
US4783730A
Cited
US5276874A
Cited
US5396632A
Cited
US5249265A
Cited
US5301287A
Cited
US5165021A
Cited
US5448702A
Cited
US5513368A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |