Patent US5838604A successfully refreshed from Google Patents.
US5838604A
Expired / Lapsed
US
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Semiconductor memory device with an increased band width
Assignee: Socionext Inc
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Filing: 1997-02-20
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Granted: 1998-11-17
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Expires: 2017-02-20
Abstract
Abstract A semiconductor memory device includes a plurality of bit lines, first sense amplifiers each connected to a corresponding one of the plurality of bit lines, and a first data bus laid out in parallel to the plurality of bit lines and connected to the plurality of bit lines via gates and the first sense amplifiers. The semiconductor memory device further includes column-selection lines laid out perpendicularly to the plurality of bit lines to open at least one of the gates to connect the first data bus to the plurality of bit lines.
Inventors
- 👤 Hironobu Tsuboi
- 👤 Yoshinori Okajima
- 👤 Tsuyoshi Higuchi
- 👤 Makoto Koga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:14
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/02; G11C5/025; G11C11/409; G11C7/00; G11C7/10
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
125 words
A semiconductor memory device comprising: a plurality of bit lines; first sense amplifiers each connected to a corresponding one of said plurality of bit lines; gates each provided for a corresponding one of said first sense amplifiers; a first data bus laid out in parallel to said plurality of bit lines and said first data bus connected to a given one of said first sense amplifiers via a corresponding one of said gates; and column-selection lines laid out perpendicularly to said plurality of bit lines and said column-selection lines opening at least one of said gates so as to select corresponding at least one of said first sense amplifiers from said first sense amplifiers arranged in a direction perpendicular to said plurality of bit lines.
Claim 2
Dependent Claim
125 words
A semiconductor memory device comprising: a plurality of bit lines; first sense amplifiers each connected to a corresponding one of said plurality of bit lines; gates each provided for a corresponding one of said first sense amplifiers; a first data bus laid out in parallel to said plurality of bit lines and said first data bus connected to a given one of said first sense amplifiers via a corresponding one of said gates; and column-selection lines laid out perpendicularly to said plurality of bit lines and said column-selection lines opening at least one of said gates so as to select corresponding at least one of said first sense amplifiers from said first sense amplifiers arranged in a direction perpendicular to said plurality of bit lines.
Claim 3
Dependent Claim
121 words
The semiconductor memory device as claimed in claim 1, further comprising: a plurality of cell blocks arranged in rows and columns and having cells connected to said bit lines, said columns extending in the same direction as said bit lines; global-column-selection lines laid out in parallel to said bit lines with respect to said columns of said cell blocks; block-selection lines laid out perpendicularly to said bit lines with respect to said rows of said cell blocks; and connection units controlled by said block-selection lines to connect between said global-column-selection lines and said column-selection lines, wherein said first sense amplifiers are arranged along said rows of said cell blocks, and said column-selection lines extend along said rows of said cell blocks.
Claim 4
Dependent Claim
32 words
The semiconductor memory device as claimed in claim 2, wherein said connection units select one of said column-selection lines based on signals on said global-column-selection lines and signals on said block-selection lines.
Claim 5
Dependent Claim
34 words
The semiconductor memory device as claimed in claim 1, further comprising sense-amplifier drivers for driving said first sense amplifiers, each of said sense-amplifier drivers provided for a corresponding one of said first sense amplifiers.
Claim 6
Dependent Claim
34 words
The semiconductor memory device as claimed in claim 1, further comprising sense-amplifier drivers for driving said first sense amplifiers, each of said sense-amplifier drivers provided for a corresponding pair of said first data bus.
Claim 7
Dependent Claim
32 words
The semiconductor memory device as claimed in claim 1, further comprising sense-amplifier drivers for driving said first sense amplifiers, each of said sense-amplifier drivers provided for a corresponding unit of column redundancy.
Claim 8
Dependent Claim
36 words
The semiconductor memory device as claimed in claim 1, further comprising power lines for shielding pairs of said first data bus from each other, said power lines laid out in parallel to said first data bus.
Claim 9
Dependent Claim
56 words
The semiconductor memory device as claimed in claim 2, further comprising: second sense amplifiers connected to said first data bus; a second data bus connected to said first data bus via said second sense amplifiers; and a decoder selectively driving said second sense amplifiers to select at least one of said columns of said cell blocks.
Claim 10
Dependent Claim
29 words
The semiconductor memory device as claimed in claim 8, wherein signals transferred via said first data bus have an amplitude smaller than a possible maximum amplitude of said signals.
Claim 11
Dependent Claim
29 words
The semiconductor memory device as claimed in claim 8, wherein signals transferred via said second data bus have an amplitude smaller than a possible maximum amplitude of said signals.
Claim 12
Dependent Claim
43 words
The semiconductor memory device as claimed in claim 8, wherein said second data bus comprises: a read-purpose data bus used for data-read purposes; and a write-purpose data bus used for data-write purposes, said write-purpose data bus being different from said read-purpose data bus.
Claim 13
Dependent Claim
32 words
The semiconductor memory device as claimed in claim 1, wherein said first data bus extends over cell block areas in which memory cells connected to said plurality of bit lines are arranged.
Claim 14
Dependent Claim
22 words
The semiconductor memory device as claimed in claim 2, wherein said global-column-selection lines are arranged between said columns of said cell blocks.
Claim 15
Dependent Claim
129 words
A semiconductor memory device carrying out bank-interleave operation, comprising: a plurality of bit lines; first sense amplifiers each connected to a corresponding one of said plurality of bit lines; gates each provided for a corresponding one of said first sense amplifiers; a first data bus laid out in parallel to said plurality of bit lines and said first data bus connected to a given one of said first sense amplifiers via a corresponding one of said gates; and column-selection lines laid out perpendicularly to said plurality of bit lines and said column-selection lines opening at least one of said gates so as to select corresponding at least one of said first sense amplifiers from said first sense amplifiers arranged in a direction perpendicular to said plurality of bit lines.
Claim 16
Dependent Claim
129 words
A semiconductor memory device carrying out bank-interleave operation, comprising: a plurality of bit lines; first sense amplifiers each connected to a corresponding one of said plurality of bit lines; gates each provided for a corresponding one of said first sense amplifiers; a first data bus laid out in parallel to said plurality of bit lines and said first data bus connected to a given one of said first sense amplifiers via a corresponding one of said gates; and column-selection lines laid out perpendicularly to said plurality of bit lines and said column-selection lines opening at least one of said gates so as to select corresponding at least one of said first sense amplifiers from said first sense amplifiers arranged in a direction perpendicular to said plurality of bit lines.
Claim 17
Dependent Claim
121 words
The semiconductor memory device as claimed in claim 14, further comprising: a plurality of cell blocks arranged in rows and columns and having cells connected to said bit lines, said columns extending in the same direction as said bit lines; global-column-selection lines laid out in parallel to said bit lines with respect to said columns of said cell blocks; block-selection lines laid out perpendicularly to said bit lines with respect to said rows of said cell blocks; and connection units controlled by said block-selection lines to connect between said global-column-selection lines and said column-selection lines, wherein said first sense amplifiers are arranged along said rows of said cell blocks, and said column-selection lines extend along said rows of said cell blocks.
Claim 18
Dependent Claim
57 words
The semiconductor device as claimed in claim 15, further comprising a row decoder successively selecting one of said block-selection lines so as to effect said bank-interleave operation with said rows of said cell blocks serving as banks, wherein said connection units connect said global-column-selection lines with said column-selection lines corresponding to said one of said block-selection lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |