US5841712A — Dual comparator circuit and method for selecting …

Claim 1

Independent Claim 125 words

A semiconductor memory having a matrix of memory elements including normal memory elements and redundant memory elements, said semiconductor memory comprising: a row predecode circuit including an enable node; redundant row selection circuitry comprising: a dynamic logic circuit implementing an N-bit wide NOT comparator coupled into a row address path of said semiconductor memory and coupled to supply said enable node with an enable signal if at least one of N row address bits mismatch a corresponding bit of a failed row address; and a logic circuit implementing an N-bit wide TRUE comparator coupled into said row address path to supply a decode signal selective for a redundant row if all of said N row address bits match corresponding bits of said failed row address.

Claim 2

Dependent Claim 125 words

A semiconductor memory having a matrix of memory elements including normal memory elements and redundant memory elements, said semiconductor memory comprising: a row predecode circuit including an enable node; redundant row selection circuitry comprising: a dynamic logic circuit implementing an N-bit wide NOT comparator coupled into a row address path of said semiconductor memory and coupled to supply said enable node with an enable signal if at least one of N row address bits mismatch a corresponding bit of a failed row address; and a logic circuit implementing an N-bit wide TRUE comparator coupled into said row address path to supply a decode signal selective for a redundant row if all of said N row address bits match corresponding bits of said failed row address.

Claim 3

Dependent Claim 34 words

A semiconductor memory, as recited in claim 1, further comprising: a row redundancy encoding corresponding to said redundant row and coupled to said NOT and said TRUE comparators to supply said failed row address.

Claim 4

Dependent Claim 21 words

A semiconductor memory, as recited in claim 2, wherein said row redundancy encoding comprises volatile storage initializable by built-in self-test logic.

Claim 5

Dependent Claim 18 words

A semiconductor memory, as recited in claim 2, wherein said row redundancy encoding comprises a fuse or anti-fuse.

Claim 6

Dependent Claim 18 words

A semiconductor memory, as recited in claim 2, wherein said row redundancy encoding comprises a floating gate MOSFET.

Claim 7

Dependent Claim 77 words

A semiconductor memory, as recited in claim 1, wherein said NOT and said TRUE comparators are coupled to enable said row predecode circuit and a redundant row predecode circuit, respectively; and wherein said row predecode circuit and said redundant row predecode circuit each couple to main row decode circuits to drive a selected word line of said matrix, said selected word line being selected by one of said row predecode circuit and said redundant row predecode circuit.

Claim 8

Dependent Claim 17 words

A semiconductor memory, as recited in claim 1, wherein said TRUE comparator is implemented in dynamic logic.

Claim 9

Dependent Claim 45 words

A semiconductor memory, as recited in claim 1, wherein said dynamic logic of said NOT comparator is responsive to a redundancy enable signal, said NOT comparator having negligible impact, when said redundancy enable signal is not asserted, on access time for said normal memory elements.

Claim 10

Dependent Claim 40 words

A semiconductor memory, as recited in claim 1, forming one of a data cache, an instruction cache, and a predecode cache of a integrated circuit microprocessor, said redundant row selection circuitry improving effective manufacturing yield of said integrated circuit microprocessor.

Claim 11

Dependent Claim 40 words

A semiconductor memory, as recited in claim 1, forming one of a data cache, an instruction cache, and a predecode cache of a integrated circuit microprocessor, said redundant row selection circuitry operable for self-repair of post shipment memory element failures.

Claim 12

Independent Claim 114 words

A method for providing redundancy in a semiconductor memory integrated circuit having normal rows and at least one redundant row, said method comprising: in response to a row address presented to said semiconductor memory, simultaneously performing in dynamic logic, TRUE and NOT comparisons of said presented row address with a failed row address; (a) enabling, in response to an affirmative NOT comparison, predecode logic associated with said normal rows; and (b) enabling, in response to an affirmative TRUE comparison, predecode logic associated with said at least one redundant row, wherein said NOT comparison is performed independently of said TRUE comparison such that timing of said (a) enabling is substantially unaffected by said TRUE comparison.

Claim 13

Independent Claim 114 words

A method for providing redundancy in a semiconductor memory integrated circuit having normal rows and at least one redundant row, said method comprising: in response to a row address presented to said semiconductor memory, simultaneously performing in dynamic logic, TRUE and NOT comparisons of said presented row address with a failed row address; (a) enabling, in response to an affirmative NOT comparison, predecode logic associated with said normal rows; and (b) enabling, in response to an affirmative TRUE comparison, predecode logic associated with said at least one redundant row, wherein said NOT comparison is performed independently of said TRUE comparison such that timing of said (a) enabling is substantially unaffected by said TRUE comparison.

Claim 14

Dependent Claim 23 words

A method, as recited in claim 11, wherein said (a) enabling is performed in dynamic non-clocked logic of said semiconductor memory integrated circuit.

Claim 15

Dependent Claim 32 words

A method, as recited in claim 11, further comprising: initializing, with built-in self-test logic, volatile storage to encode said failed row address; and supplying said failed row address from said volatile storage.

Claim 16

Dependent Claim 81 words

An integrated circuit chip comprising: an array of semiconductor memory elements including normal and redundant memory elements; a rewritable on chip encoding to encode a failed address corresponding to a redundant group of said redundant memory elements; a TRUE comparator circuit coupled to select said redundant group when an address supplied to said array corresponds to said failed address; and a dynamic NOT comparator circuit coupled to enable address decode circuits when said address does not correspond to said failed address.

Claim 17

Dependent Claim 81 words

An integrated circuit chip comprising: an array of semiconductor memory elements including normal and redundant memory elements; a rewritable on chip encoding to encode a failed address corresponding to a redundant group of said redundant memory elements; a TRUE comparator circuit coupled to select said redundant group when an address supplied to said array corresponds to said failed address; and a dynamic NOT comparator circuit coupled to enable address decode circuits when said address does not correspond to said failed address.

Claim 18

Dependent Claim 22 words

An integrated circuit chip, as recited in claim 14, wherein said redundant group comprises a redundant word line of redundant memory elements.

Claim 19

Dependent Claim 21 words

An integrated circuit chip, as recited in claim 14, wherein said redundant group comprises a redundant row of redundant memory elements.

Claim 20

Dependent Claim 21 words

An integrated circuit chip, as recited in claim 14, wherein said redundant group comprises a redundant column of redundant memory elements.

Claim 21

Dependent Claim 32 words

An integrated circuit chip, as recited in claim 14, wherein said integrated circuit chip comprises an integrated circuit microprocessor chip with a cache memory block defining said array of semiconductor memory elements.

Claim 22

Dependent Claim 30 words

An integrated circuit chip, as recited in claim 14, wherein said integrated circuit chip comprises a memory chip with a memory block thereon defining said array of semiconductor memory elements.

Claim 23

Dependent Claim 41 words

An integrated circuit chip, as recited in claim 14, coupled into a computer system having a processor, a memory and a bus coupled therebetween, said packaged integrated circuit chip including circuits of at least one of said processor and said memory.

Claim 24

Independent Claim 119 words

An apparatus comprising: a semiconductor memory array; row predecoder means coupled to at least partially decode a row address into said semiconductor memory array, said row predecoder means including a first enable terminal; redundant row selection means including a second enable terminal; NOT comparator means coupled into a row address path of said semiconductor memory and coupled to supply said first enable terminal with an enable signal if said row address mismatches a failed row address encoding; and TRUE comparator means distinct from said NOT comparator means and coupled into said row address path to supply via said redundant row selection means, a decode signal selective for a redundant row if said row address matches said failed row encoding.

Claim 25

Independent Claim 119 words

An apparatus comprising: a semiconductor memory array; row predecoder means coupled to at least partially decode a row address into said semiconductor memory array, said row predecoder means including a first enable terminal; redundant row selection means including a second enable terminal; NOT comparator means coupled into a row address path of said semiconductor memory and coupled to supply said first enable terminal with an enable signal if said row address mismatches a failed row address encoding; and TRUE comparator means distinct from said NOT comparator means and coupled into said row address path to supply via said redundant row selection means, a decode signal selective for a redundant row if said row address matches said failed row encoding.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-11-23	2002-05-25	2002-11-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-11-23	2006-05-25	2006-11-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-11-23	2010-05-25	2010-11-24	$7700.00	Window Closed / Lapsed

Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device

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