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US5848009A
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Integrated circuit memory devices that map nondefective memory cell blocks into continuous addresses
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-10-07
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Granted: 1998-12-08
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Expires: 2017-10-07
Abstract
Abstract Integrated circuit memory devices and operating methods map a plurality of memory cell blocks excluding defective memory cell blocks into a continuous address sequence of variable length. The memory cell blocks excluding the defective memory cell blocks, are preferably mapped to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower cell block addresses, so as to generate continuous addresses for the memory cell blocks. Continuous address spaces may be provided by providing a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks. Each flag block contains a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, or a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block. Then, upon addressing a normal memory cell block, a redundant memory cell block is substituted if the second indication is in the flag block that is associated with the selected normal memory cell block. A nondefective normal memory cell block is substituted for a selected normal cell block in response to the third indication being in the flag block that is associated with the selected normal memory cell block.
Inventors
- 👤 Sung-Soo Lee
- 👤 Young-Ho Lim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
66 words
An integrated circuit memory device comprising: a plurality of normal memory cell blocks; a plurality of redundant memory cell blocks; and means for substituting nondefective normal memory cell blocks for defective normal memory cell blocks that remain after substitution of the plurality of redundant memory cell blocks for defective normal memory cell blocks, so as to generate continuous addresses for the nondefective normal memory cell blocks.
Claim 2
Dependent Claim
66 words
An integrated circuit memory device comprising: a plurality of normal memory cell blocks; a plurality of redundant memory cell blocks; and means for substituting nondefective normal memory cell blocks for defective normal memory cell blocks that remain after substitution of the plurality of redundant memory cell blocks for defective normal memory cell blocks, so as to generate continuous addresses for the nondefective normal memory cell blocks.
Claim 3
Dependent Claim
77 words
An integrated circuit memory device according to claim 1 wherein the substituting means sequentially substitutes nondefective normal memory cell blocks, beginning at a highest nondefective normal memory cell block address and sequentially proceeding to lower nondefective memory cell block addresses, for defective normal memory cell blocks that remain after substitution of the plurality of redundant memory cell blocks for defective normal memory cell blocks, so as to generate continuous addresses for the nondefective normal memory cell blocks.
Claim 4
Dependent Claim
31 words
An integrated circuit memory device according to claim 1 wherein the substituting means further comprises: means for substituting the plurality of redundant memory cell blocks for defective normal memory cell blocks.
Claim 5
Dependent Claim
41 words
An integrated circuit memory device comprising: a plurality of memory cell blocks including defective memory cell blocks; and means for mapping the plurality of memory cell blocks excluding the defective memory cell blocks into a continuous address sequence of variable length.
Claim 6
Dependent Claim
41 words
An integrated circuit memory device comprising: a plurality of memory cell blocks including defective memory cell blocks; and means for mapping the plurality of memory cell blocks excluding the defective memory cell blocks into a continuous address sequence of variable length.
Claim 7
Dependent Claim
58 words
An integrated circuit memory device according to claim 4 wherein the mapping means sequentially maps memory cell blocks excluding the defective memory cell blocks to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower memory cell block addresses, so as to generate continuous addresses for the memory cell blocks.
Claim 8
Dependent Claim
177 words
An integrated circuit memory device comprising: a plurality of normal memory cell blocks; a plurality of redundant memory cell blocks; a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks, each flag block containing one of a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, and a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block; and means, responsive to the plurality of flag blocks, for substituting a redundant memory cell block for a selected normal memory cell block in response to the second indication being in a flag block that is associated with the selected normal memory cell block and for substituting a nondefective normal memory cell block for a selected normal memory cell block in response to the third indication being in a flag block that is associated with the selected normal memory cell block.
Claim 9
Dependent Claim
177 words
An integrated circuit memory device comprising: a plurality of normal memory cell blocks; a plurality of redundant memory cell blocks; a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks, each flag block containing one of a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, and a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block; and means, responsive to the plurality of flag blocks, for substituting a redundant memory cell block for a selected normal memory cell block in response to the second indication being in a flag block that is associated with the selected normal memory cell block and for substituting a nondefective normal memory cell block for a selected normal memory cell block in response to the third indication being in a flag block that is associated with the selected normal memory cell block.
Claim 10
Dependent Claim
124 words
An integrated circuit memory device according to claim 6: wherein the second indication comprises a plurality of second indications and wherein the third indication comprises a plurality of third indications; the substituting means comprising means, responsive to the plurality of flag blocks, for substituting a selected redundant memory cell block for a selected normal memory cell block in response to a selected one of the second indications being in a flag block that is associated with the selected normal memory cell block and for substituting a selected nondefective normal memory cell block for a selected normal memory cell block in response to a selected one of the third indications being in a flag block that is associated with the selected normal memory cell block.
Claim 11
Dependent Claim
151 words
An integrated circuit memory device according to claim 6 wherein each of the flag blocks comprises: a plurality of flag cell strings, each comprising a plurality of flag cell transistors that are serially connected between a pair of flag cell string selection transistors, the flag cell strings storing the one of a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, and a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block; a plurality of flag word lines, a respective one of which is connected to a corresponding flag cell transistor in each of the flag cell strings; and a plurality of flag bit lines, a respective one of which is connected to at least one of the flag cell string selection transistors.
Claim 12
Dependent Claim
84 words
An integrated circuit memory device according to claim 8 wherein selected ones of the plurality of flag cell strings in a flag cell block are electrically connected in parallel, and store a same one of a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, and a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block.
Claim 13
Dependent Claim
87 words
An integrated circuit memory device according to claim 6 wherein the substituting means comprises: a sense amplifier that detects the indication that is stored in a selected flag block and generates a defective block status signal therefrom; a flag decoder that is responsive to the defective block status signal to generate a repair block selection signal; and a block selection controller that is responsive to the block status signal to disable a row decoder so that the row decoder does not select a normal memory cell block.
Claim 14
Independent Claim
75 words
A method of operating an integrated circuit memory device including a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, the operating method comprising the step of: substituting nondefective normal memory cell blocks for defective normal memory cell blocks that remain after substitution of the plurality of redundant memory cell blocks for defective normal memory cell blocks, so as to generate continuous addresses for the nondefective normal memory cell blocks.
Claim 15
Independent Claim
75 words
A method of operating an integrated circuit memory device including a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, the operating method comprising the step of: substituting nondefective normal memory cell blocks for defective normal memory cell blocks that remain after substitution of the plurality of redundant memory cell blocks for defective normal memory cell blocks, so as to generate continuous addresses for the nondefective normal memory cell blocks.
Claim 16
Dependent Claim
78 words
A method according to claim 11 wherein the substituting step comprises the step of sequentially substituting nondefective normal memory cell blocks, beginning at a highest nondefective normal memory cell block address and sequentially proceeding to lower nondefective memory cell block addresses, for defective normal memory cell blocks that remain after substitution of the plurality of redundant memory cell blocks for defective normal memory cell blocks, so as to generate continuous addresses for the nondefective normal memory cell blocks.
Claim 17
Dependent Claim
30 words
A method according to claim 12 wherein the substituting step is preceded by the step of: substituting the plurality of redundant memory cell blocks for defective normal memory cell blocks.
Claim 18
Independent Claim
49 words
A method of operating an integrated circuit memory device comprising a plurality of memory cell blocks including defective memory cell blocks, the operating method comprising the step of: mapping the plurality of memory cell blocks excluding the defective memory cell blocks into a continuous address sequence of variable length.
Claim 19
Independent Claim
49 words
A method of operating an integrated circuit memory device comprising a plurality of memory cell blocks including defective memory cell blocks, the operating method comprising the step of: mapping the plurality of memory cell blocks excluding the defective memory cell blocks into a continuous address sequence of variable length.
Claim 20
Dependent Claim
59 words
A method according to claim 14 wherein the mapping step comprises the step of sequentially mapping memory cell blocks excluding the defective memory cell blocks to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower memory cell block addresses, so as to generate continuous addresses for the memory cell blocks.
Claim 21
Independent Claim
166 words
A method of operating an integrated circuit memory device including a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, the operating method comprising the steps of: for each normal memory cell block, storing in the integrated circuit memory device one of a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, and a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block; substituting a redundant memory cell block for a selected normal memory cell block in response to the second indication being in a flag block that is associated with the selected normal memory cell block; and substituting a nondefective normal memory cell block for a selected normal memory cell block in response to the third indication being in a flag block that is associated with the selected normal memory cell block.
Claim 22
Independent Claim
166 words
A method of operating an integrated circuit memory device including a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, the operating method comprising the steps of: for each normal memory cell block, storing in the integrated circuit memory device one of a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, and a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block; substituting a redundant memory cell block for a selected normal memory cell block in response to the second indication being in a flag block that is associated with the selected normal memory cell block; and substituting a nondefective normal memory cell block for a selected normal memory cell block in response to the third indication being in a flag block that is associated with the selected normal memory cell block.
Claim 23
Dependent Claim
27 words
A method according to claim 16: wherein the second indication comprises a plurality of second indications and wherein the third indication comprises a plurality of third indications.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |