Symbol timing recovery circuit and method

Claim 2

A symbol timing recovery circuit of a digital television, comprising: analog-to-digital converting means for sampling a received analog signal by a symbol clock to be converted to digital data; demodulating means for recovering a carrier wave, demodulating said digital data to a baseband signal and generating a segment signal; segment synchronizing signal detecting means for detecting a segment synchronizing signal from said segment signal; phase error detecting means for receiving said segment signal and detecting a phase error from synchronizing symbols of said segment synchronizing signal, said phase error detecting means being activated by said segment synchronizing signal; and symbol clock phase adjusting means for adjusting the phase of said symbol clock according to said phase error of said synchronizing symbols to be supplied to said analog-to-digital converting means as said symbol clock.

Claim 3

A symbol timing recovery circuit of a digital television as set forth in claim 1, wherein said phase error detecting means comprises: means for delaying said segment signal and again delaying the delayed segment signal to generate first and second delayed segment signals; means for detecting a phase error of two segment signals by calculating a difference between said first and second delayed segment signals; and switching means for switching said phase error, said switching means being activated by said segment synchronizing signal.

Claim 4

A symbol timing recovery circuit of a digital television as set forth in claim 2, wherein said symbol clock phase adjusting means comprises: a loop filter for accumulating said phase error and scaling the accumulated phase error to a control voltage level; digital-to-analog converting means for converting an output of said loop filter to an analog control voltage; and oscillating means for adjusting the phase of said symbol clock, said oscillating means being oscillated by said analog control voltage.

Claim 5

A symbol timing recovery circuit of a digital television as set forth in any one of claims 1 to 3, wherein said segment synchronizing signal detecting means comprises: accumulating means for delaying received data segment signals by a segment period and accumulating the delayed segment signals; synchronizing signal correlating means for delaying an output of said accumulating means by a synchronizing signal period, multiplying each delayed synchronizing signal by a correlation value of a corresponding synchronizing signal, adding each multiplied synchronizing signal, and detecting a segment synchronizing signal having a peak value at said synchronizing signal period; and means for comparing an output of said synchronizing signal correlating means with an internal reference value to generate a segment synchronizing signal.

Claim 6

A symbol timing recovery circuit of a digital television in which one segment signal has a synchronizing signal of first to fourth symbols and data of 828 symbols, said first and fourth synchronizing symbols are transmitted with a first signal level, and said second and third synchronizing symbols are transmitted with a second signal level, said symbol timing recovery circuit comprising: analog-to-digital converting means for sampling a received analog signal by a symbol clock to be converted to digital data; demodulating means for recovering a carrier wave, demodulating said digital data to a baseband signal and generating a segment signal; segment synchronizing signal detecting means for detecting a segment synchronizing signal from said segment signal; phase error detecting means for receiving said segment signal and detecting a phase error by a difference between said second and third synchronizing symbols, said phase error detecting means being activated by said segment synchronizing signal; and symbol clock phase adjusting means for adjusting the phase of said symbol clock according to said phase error of said synchronizing symbols to be supplied to said analog-to-digital converting means as said symbol clock.

Claim 7

A symbol timing recovery circuit of a digital television in which one segment signal has a synchronizing signal of first to fourth symbols and data of 828 symbols, said first and fourth synchronizing symbols are transmitted with a first signal level, and said second and third synchronizing symbols are transmitted with a second signal level, said symbol timing recovery circuit comprising: analog-to-digital converting means for sampling a received analog signal by a symbol clock to be converted to digital data; demodulating means for recovering a carrier wave, demodulating said digital data to a baseband signal and generating a segment signal; segment synchronizing signal detecting means for detecting a segment synchronizing signal from said segment signal; phase error detecting means for receiving said segment signal and detecting a phase error by a difference between said second and third synchronizing symbols, said phase error detecting means being activated by said segment synchronizing signal; and symbol clock phase adjusting means for adjusting the phase of said symbol clock according to said phase error of said synchronizing symbols to be supplied to said analog-to-digital converting means as said symbol clock.

Claim 8

A symbol timing recovery circuit of a digital television as set forth in claim 5, wherein said phase error detecting means comprises: means for delaying said segment signal and again delaying the delayed segment signal to generate first and second delayed segment signals; means for detecting a phase error of two segment signals by calculating a difference between said first and second delayed segment signals; and switching means for switching said phase error, said switching means being activated by said segment synchronizing signal.

Claim 9

A symbol timing recovery circuit of a digital television as set forth in claim 6, wherein said symbol clock phase adjusting means comprises: a loop filter for accumulating said phase error and scaling the accumulated phase error to a control voltage level; digital-to-analog converting means for converting an output of said loop filter to an analog control voltage; and oscillating means for adjusting the phase of said symbol clock, said oscillating means being oscillated by said analog control voltage.

Claim 10

A symbol timing recovery circuit of a digital television as set forth in any one of claims 5 to 7, wherein said segment synchronizing signal detecting means comprises: accumulating means having a segment delay, for adding said segment signal to the delayed segment signal generated from said segment delay; means having first to fourth delays, for delaying an output of said accumulating means to generate first to fourth delay symbol signals; means having first to fourth multipliers, for respectively multiplying said first to fourth delay symbol signals by a correlation value of a corresponding synchronizing signal; adding means for adding outputs of said first to fourth multipliers and generating a peak value at a synchronizing signal period; and means for comparing an output of said adding means with an internal reference value to generate a segment synchronizing.

Claim 11

A symbol timing recovery method of a digital television in which one segment signal has a synchronizing signal of first to fourth symbols and data of 828 symbols, said first and fourth synchronizing symbols are transmitted with a first signal level, and said second and third synchronizing symbols are transmitted with a second signal level, said symbol timing recovery method comprising the steps of: sampling a received analog signal by a symbol clock to be converted to digital data; recovering a carrier wave, demodulating said digital data to a baseband signal and generating a segment signal; detecting a segment synchronizing signal from said segment signal; detecting a phase error between said second and third synchronizing symbols by said segment synchronizing signal; and adjusting the phase of said symbol clock according to said phase error of said synchronizing symbols and supplying the phase-adjusted symbol clock to said sampling step.

Claim 12

A symbol timing recovery method of a digital television in which one segment signal has a synchronizing signal of first to fourth symbols and data of 828 symbols, said first and fourth synchronizing symbols are transmitted with a first signal level, and said second and third synchronizing symbols are transmitted with a second signal level, said symbol timing recovery method comprising the steps of: sampling a received analog signal by a symbol clock to be converted to digital data; recovering a carrier wave, demodulating said digital data to a baseband signal and generating a segment signal; detecting a segment synchronizing signal from said segment signal; detecting a phase error between said second and third synchronizing symbols by said segment synchronizing signal; and adjusting the phase of said symbol clock according to said phase error of said synchronizing symbols and supplying the phase-adjusted symbol clock to said sampling step.