US5864656A
Expired / Lapsed
US
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System for automatic fault detection and recovery in a computer system
Assignee: Hanger Solutions LLC
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Filing: 1997-06-30
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Granted: 1999-01-26
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Expires: 2017-06-30
Abstract
Abstract A system for automatic fault detection and recovery in a computer system includes: a system fault detector, a halt time duration counter, and program and hardware recovery signal generators. The system fault detector is connected to a plurality of bus signal lines of a computer system to produce an output signal in response to an existence of an operating signal in the system bus. The halt time counter is operated in response to the output signal of the fault detector and clock signals to produce a set of count values each representing the passage of a predetermined time duration after a vanishing of the output signal of the fault detector. The program recovery signal generator produces a system management interrupt (SMI) signal when seven minutes have elapsed from the detection of the system halt. Also, the hardware recovery signal generator produces a reset signal when eight minutes have elapsed from the detection of the system halt. Further, the recovery system includes a selector consisting of a one-bit register for storing an initial value for enabling operation of the fault detector at the start of the computer system, the selector being connected to the system bus and changing its initial value in response to a BIOS program from the system bus to disable the operation of the fault detector. The computer system is set to save the data processed in an application program in response to the SMI signal.
Inventors
- 👤 Jee-kyoung Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:35
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1438; G06F11/30; G06F11/34; G06F11/3466; G06F11/349
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
254 words
A system for automatic fault detection and recovery in a computer system comprising: a system fault detector connected to a plurality of bus signal lines of a computer system for producing an output signal in response to an operating signal from the system bus; a halt time counter for counting clock signals in response to the output signal of the fault detector to produce a set of count values, each representing a passage of a predetermined time duration after a vanishing of the output signal of the fault detector; a program recovery signal generator for producing a first interrupt signal when the count values received from the halt time counter reach a preset first count value, the first interrupt signal being inputted to the computer system to effect a program recovery process; a hardware recovery signal generator for producing a second interrupt signal when the count values received from the halt time counter reach a preset second count value, the time duration corresponding to the second count value being longer than that of the first count value, the second interrupt signal being inputted to the computer system to effect a hardware recovery process; and a selector, connected to the system fault detector for storing an initial value for enabling operation of the fault detector at the start of the computer system, the selector being connected to the system bus and the selector changing its initial value in response to a BIOS program from the system bus to disable the operation of the fault detector.
Claim 2
Independent Claim
254 words
A system for automatic fault detection and recovery in a computer system comprising: a system fault detector connected to a plurality of bus signal lines of a computer system for producing an output signal in response to an operating signal from the system bus; a halt time counter for counting clock signals in response to the output signal of the fault detector to produce a set of count values, each representing a passage of a predetermined time duration after a vanishing of the output signal of the fault detector; a program recovery signal generator for producing a first interrupt signal when the count values received from the halt time counter reach a preset first count value, the first interrupt signal being inputted to the computer system to effect a program recovery process; a hardware recovery signal generator for producing a second interrupt signal when the count values received from the halt time counter reach a preset second count value, the time duration corresponding to the second count value being longer than that of the first count value, the second interrupt signal being inputted to the computer system to effect a hardware recovery process; and a selector, connected to the system fault detector for storing an initial value for enabling operation of the fault detector at the start of the computer system, the selector being connected to the system bus and the selector changing its initial value in response to a BIOS program from the system bus to disable the operation of the fault detector.
Claim 3
Dependent Claim
12 words
The system according to claim 1, the selector comprising a one-bit register.
Claim 4
Dependent Claim
37 words
The system according to claim 1, the system fault detector comprising an AND gate having a plurality of inputs connected to a plurality of bus lines and an inverter input connected to the output of the selector.
Claim 5
Dependent Claim
36 words
The system according to claim 1, the halt time counter comprising a timer having a clear input for receiving the output signal of the fault detector, and four outputs for producing the set of count values.
Claim 6
Dependent Claim
24 words
The system according to claim 4, the halt time counter outputting one counter value for a number of clock signals corresponding to one minute.
Claim 7
Dependent Claim
24 words
The system according to claim 1, the halt time counter outputting one counter value for a number of clock signals corresponding to one minute.
Claim 8
Dependent Claim
46 words
The system according to claim 1, the program recovery signal generator comprising a first NAND gate having a plurality of inputs each connected to the outputs of the halt time counter so that the gate produces a logical "0" output signal as the first interrupt signal.
Claim 9
Dependent Claim
47 words
The system according to claim 7, the hardware recovery signal generator comprising a second NAND gate having inputs respectively connected in parallel with the inputs of the first NAND gate so that the second NAND gate produces a logical "0" output signal as the second interrupt signal.
Claim 10
Dependent Claim
31 words
The system according to claim 1, the first interrupt signal comprising a system management interrupt (SMI) signal for causing the computer system to save the data processed in an application program.
Claim 11
Dependent Claim
23 words
The system according to claim 1, the second interrupt signal comprising a system reset signal for causing a rebooting of the computer system.
Claim 12
Independent Claim
194 words
A system for automatic fault detection and recovery in a computer system comprising: a system default detector connected to a plurality of bus signal lines of a computer system for producing an output signal in response to an operating signal from the system bus; a halt time counter for counting clock signals in response to the output signal of the fault detector to produce a set of count values, each representing a passage of a predetermined time duration after a vanishing of the output signal of the fault detector; a program recovery signal generator for producing a first interrupt signal when the count values received from the halt time counter reach a preset first count value, the first interrupt signal being inputted to the computer system to effect a program recovery process; and a hardware recovery signal generator for producing a second interrupt signal when the count values received from the halt time counter reach a preset second count value, the time duration corresponding to the second count value being longer than that of the first count value, the second interrupt signal being inputted to the computer system to effect a hardware recovery process.
Claim 13
Independent Claim
194 words
A system for automatic fault detection and recovery in a computer system comprising: a system default detector connected to a plurality of bus signal lines of a computer system for producing an output signal in response to an operating signal from the system bus; a halt time counter for counting clock signals in response to the output signal of the fault detector to produce a set of count values, each representing a passage of a predetermined time duration after a vanishing of the output signal of the fault detector; a program recovery signal generator for producing a first interrupt signal when the count values received from the halt time counter reach a preset first count value, the first interrupt signal being inputted to the computer system to effect a program recovery process; and a hardware recovery signal generator for producing a second interrupt signal when the count values received from the halt time counter reach a preset second count value, the time duration corresponding to the second count value being longer than that of the first count value, the second interrupt signal being inputted to the computer system to effect a hardware recovery process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |