Patent US5872904A successfully refreshed from Google Patents.
US5872904A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system using a master processor to automatically reconfigure faulty switch node that is detected and reported by diagnostic processor without causing communications interruption
Assignee: Teradata US Inc
•
Filing: 1996-05-24
•
Granted: 1999-02-16
•
Expires: 2016-05-24
Abstract
Abstract A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 +539 logb N +538 stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and +539 logb N +538 indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
Inventors
- 👤 Robert J. McMillen
- 👤 M. Cameron Watson
- 👤 David J. Chura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:31
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2002; G06F11/2005; G01; G01J; G01J3/00; G01J3/02; G01J3/06; G06F11/14; G06F11/1402; G06F11/1415; G06F11/142; G06F11/1423; G06F11/22; H; H04; H04L; H04L49/00; H04L49/15; H04L49/1515; H04L49/35; H04L49/356; H04L49/358; H04L49/55; H04L49/552; H04L49/555; H04L49/557; H04Q; H04Q3/00; H04Q3/64; H04Q3/68; G06F11/2007; G06F2201/00; G06F2201/85; H04Q2213/00; H04Q2213/13332
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
129 words
A method of communications in a computer system, comprising the steps of: (a) transmitting messages between a plurality of processors in the computer system using a plurality of separate and distinct networks, wherein each of the networks is comprised of a plurality of active logic switch nodes; (b) detecting and reporting any errors that occur within each of the networks during the transmitting step using one or more diagnostic processors coupled to the switch nodes; and (c) automatically reconfiguring one or more switch nodes in one of the networks using a master processor coupled to the diagnostic processors when an error is detected in the network, while using only the other one of the networks for transmitting messages during the reconfiguration step to avoid interrupting communications in the system.
Claim 2
Independent Claim
129 words
A method of communications in a computer system, comprising the steps of: (a) transmitting messages between a plurality of processors in the computer system using a plurality of separate and distinct networks, wherein each of the networks is comprised of a plurality of active logic switch nodes; (b) detecting and reporting any errors that occur within each of the networks during the transmitting step using one or more diagnostic processors coupled to the switch nodes; and (c) automatically reconfiguring one or more switch nodes in one of the networks using a master processor coupled to the diagnostic processors when an error is detected in the network, while using only the other one of the networks for transmitting messages during the reconfiguration step to avoid interrupting communications in the system.
Claim 3
Dependent Claim
61 words
The method of claim 1, wherein each of the switch nodes further comprises a tag mapping table associated with each input port of a switch node, and the method further comprises the step of interpreting a routing tag to determine which output port of the switch node to select in order to route a connect request correctly through the reconfigured network.
Claim 4
Dependent Claim
61 words
The method of claim 2, wherein the tag mapping table comprises a memory array with a plurality of entries, and the method further comprises the step of translating the routing tag to an output port selection, wherein the memory array provides a one-to-one mapping between a logical output port selection provided by the routing tag and a physical output port selection.
Claim 5
Dependent Claim
37 words
The method of claim 3, further comprising the step of deriving each entry in the memory array from an appropriate field of the routing tag according to a stage of the switch node within the reconfigured network.
Claim 6
Dependent Claim
38 words
The method of claim 2, wherein the method further comprises the step of mapping the routing tag to a physical output port selection based on the way in which the switch nodes in the reconfigured network are interconnected.
Claim 7
Dependent Claim
48 words
The method of claim 2, further comprising the step of initializing each entry in the tag mapping table with a default value, so that a physical output port selection is equal to a logical output port selection, thereby providing default values that are appropriate for fully configured networks.
Claim 8
Dependent Claim
36 words
The method of claim 6, further comprising the step of overlaying the default values when the master processor coupled to the reconfigured network has determined an actual topology for the switch nodes in the reconfigured network.
Claim 9
Dependent Claim
24 words
The method of claim 1, further comprising the step of indicating which input ports of the switch node are operational via input enable vectors.
Claim 10
Dependent Claim
24 words
The method of claim 1, further comprising the step of indicating which output ports of the switch node are operational via output enable vectors.
Claim 11
Dependent Claim
121 words
A computer system, comprising: (a) a plurality of processors transmitting messages therebetween using a plurality of separate and distinct networks, wherein each of the networks is comprised of a plurality of active logic switch nodes; (b) one or more diagnostic processors, coupled to the switch nodes, for detecting and reporting any errors that occur within each of the networks during the transmitting of messages; and (c) a master processor, coupled to the diagnostic processors, for automatically reconfiguring one or more switch nodes in one of the networks via the diagnostic processors when an error is detected in the network, while using only the other one of the networks for transmitting messages during the reconfiguration to avoid interrupting communications in the system.
Claim 12
Dependent Claim
121 words
A computer system, comprising: (a) a plurality of processors transmitting messages therebetween using a plurality of separate and distinct networks, wherein each of the networks is comprised of a plurality of active logic switch nodes; (b) one or more diagnostic processors, coupled to the switch nodes, for detecting and reporting any errors that occur within each of the networks during the transmitting of messages; and (c) a master processor, coupled to the diagnostic processors, for automatically reconfiguring one or more switch nodes in one of the networks via the diagnostic processors when an error is detected in the network, while using only the other one of the networks for transmitting messages during the reconfiguration to avoid interrupting communications in the system.
Claim 13
Dependent Claim
62 words
The computer system of claim 10, wherein each of the switch nodes further comprises a tag mapping table associated with each input port of a switch node, and the switch nodes further comprising means for interpreting a routing tag to determine which output port of the switch node to select in order to route a connect request correctly through the reconfigured network.
Claim 14
Dependent Claim
62 words
The computer system of claim 11, wherein the tag mapping table comprises a memory array with a plurality of entries, and the switch nodes further comprising means for translating the routing tag to an output port selection, wherein the memory array provides a one-to-one mapping between a logical output port selection provided by the routing tag and a physical output port selection.
Claim 15
Dependent Claim
41 words
The computer system of claim 12, wherein the switch nodes further comprise means for deriving each entry in the memory array from an appropriate field of the routing tag according to a stage of the switch node within the reconfigured network.
Claim 16
Dependent Claim
39 words
The computer system of claim 11, wherein the switch nodes further comprises means for mapping the routing tag to a physical output port selection based on the way in which the switch nodes in the reconfigured network are interconnected.
Claim 17
Dependent Claim
52 words
The computer system of claim 11, wherein the switch nodes further comprise means for initializing each entry in the tag mapping table with a default value, so that a physical output port selection is equal to a logical output port selection, thereby providing default values that are appropriate for fully configured networks.
Claim 18
Dependent Claim
35 words
The computer system of claim 15, wherein the diagnostic processors further comprise means for overlaying the default values when the master processor has determined an actual topology for the switch nodes in the reconfigured network.
Claim 19
Dependent Claim
26 words
The computer system of claim 10, wherein the switch nodes further comprise input enable vectors for indicating which input ports of the switch node are operational.
Claim 20
Dependent Claim
26 words
The computer system of claim 10, wherein the switch nodes further comprise output enable vectors for indicating which output ports of the switch node are operational.
References Cited (Backward Citations)
US3317676A
Cited
US3290446A
Cited
US3491211A
Cited
US3582560A
Cited
US3581286A
Cited
US3693155A
Cited
US3963872A
Cited
US4022982A
Cited
US4081612A
Cited
US4075693A
Cited
US4074072A
Cited
US4038638A
Cited
US4177514A
Cited
US4173713A
Cited
US4146749A
Cited
US4201891A
Cited
US4201889A
Cited
US4247892A
Cited
US4707781A
Cited
US4484262A
Cited
US4237447A
Cited
US4251879A
Cited
US4307446A
Cited
US4347498A
Cited
US4317193A
Cited
US4344134A
Cited
US4412285A
Cited
US5006978A
Cited
US4814979A
Cited
US4445171A
Cited
US4945471A
Cited
US4956772A
Cited
US4543630A
Cited
US4494185A
Cited
US4417244A
Cited
US4417245A
Cited
US4466060A
Cited
US4456987A
Cited
US4638475A
Cited
US4486877A
Cited
US4491945A
Cited
US4622632A
Cited
US4518960A
Cited
US4481623A
Cited
US4523273A
Cited
US4561090A
Cited
US4814973A
Cited
US4540000A
Cited
US4550397A
Cited
US4577308A
Cited
US4633394A
Cited
US4695999A
Cited
US4706150A
Cited
US4679186A
Cited
US4661947A
Cited
US4656622A
Cited
US4621359A
Cited
US4630258A
Cited
US4623996A
Cited
US4651318A
Cited
US4742511A
Cited
US4701906A
Cited
US4630260A
Cited
US4670871A
Cited
US4663620A
Cited
US4734907A
Cited
US4829227A
Cited
US4847755A
Cited
US4811210A
Cited
US4731878A
Cited
US4731825A
Cited
US4925311A
Cited
US4814980A
Cited
US4780873A
Cited
US4860201A
Cited
US4766534A
Cited
US4817084A
Cited
US4845744A
Cited
US4785446A
Cited
US4745593A
Cited
US4864558A
Cited
US4761780A
Cited
US4740954A
Cited
US4782478A
Cited
US4809362A
Cited
US4849751A
Cited
US4833468A
Cited
US4845722A
Cited
US4833671A
Cited
US5022025A
Cited
US4845736A
Cited
US4866701A
Cited
US5214642A
Cited
US5199027A
Cited
US5088091A
Cited
US5119369A
Cited
US4962497A
Cited
US5121384A
Cited
US5522046A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |