Patent US5880508A successfully refreshed from Google Patents.
US5880508A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOSFET with a high permitivity gate dielectric
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1998-07-29
•
Granted: 1999-03-09
•
Expires: 2018-07-29
Abstract
Abstract A transistor formed on a semi-conductor substrate, where the transistor includes a gate dielectric layer formed on the semi-conductor substrate. The gate dielectric layer includes a silicon oxynitride sub-layer formed on the semi-conductor substrate and a dielectric sub-layer having relatively high permitivity to an oxide formed on the silicon oxynitride sub-layer. The transistor also includes a barrier layer formed on the gate dielectric layer and a metal gate is formed on the barrier layer. The gate dielectric layer, the barrier layer and the metal gate combine to form a gate structure. Side walls spacers are formed on side walls of the gate structure, and extended source, drain junctions are formed under the side wall spacers in the semi-conductor substrate and adjacent to the gate structure. The transistor also includes source and drain junctions formed in the gate structure next to the extended source, drain junctions.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:24
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01318; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/01344; H10D64/60; H10D64/66; H10D64/667; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693; H10P; H10P32/00; H10P32/10; H10P32/12; H10P32/1204
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
129 words
A transistor formed on a semiconductor substrate, said transistor comprising: a gate dielectric layer formed on said semiconductor substrate, said gate dielectric layer including a silicon oxynitride sub-layer formed on said semiconductor substrate, a dielectric sub-layer having relatively high permitivity to an oxide formed on said silicon oxynitride sub-layer; a barrier layer formed on said gate dielectric layer; a metal gate formed on said barrier layer, said gate dielectric layer, said barrier layer and said metal gate forming a gate structure; side wall spacers formed on side walls of said gate structure; extended source, drain junctions formed under said side wall spacers, in said semiconductor substrate and adjacent to said gate structure; and source and drain junctions formed in said gate structure next to said extended source, drain junctions.
Claim 2
Dependent Claim
129 words
A transistor formed on a semiconductor substrate, said transistor comprising: a gate dielectric layer formed on said semiconductor substrate, said gate dielectric layer including a silicon oxynitride sub-layer formed on said semiconductor substrate, a dielectric sub-layer having relatively high permitivity to an oxide formed on said silicon oxynitride sub-layer; a barrier layer formed on said gate dielectric layer; a metal gate formed on said barrier layer, said gate dielectric layer, said barrier layer and said metal gate forming a gate structure; side wall spacers formed on side walls of said gate structure; extended source, drain junctions formed under said side wall spacers, in said semiconductor substrate and adjacent to said gate structure; and source and drain junctions formed in said gate structure next to said extended source, drain junctions.
Claim 3
Dependent Claim
16 words
The transistor of claim 1, further comprises a anti-refractive coating layer formed on said metal gate.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein said dielectric sub-layer comprises TiO 2 .
Claim 5
Dependent Claim
15 words
The transistor of claim 1, wherein said dielectric sub-layer comprises Ta 2 O 5 .
Claim 6
Dependent Claim
11 words
The transistor of claim 1, wherein said dielectric sub-layer comprises PZT.
Claim 7
Dependent Claim
11 words
The transistor of claim 1, wherein said dielectric sub-layer comprises BST.
Claim 8
Dependent Claim
11 words
The transistor of claim 1, wherein said barrier gate comprises TiN.
Claim 9
Dependent Claim
11 words
The transistor of claim 1, wherein said metal gate comprises titanium.
Claim 10
Dependent Claim
11 words
The transistor of claim 1, wherein said metal gate comprises tungsten.
Claim 11
Dependent Claim
11 words
The transistor of claim 2, wherein said anti-refractive coating comprises TiN.
References Cited (Backward Citations)
US5464783A
Cited
US5484783A
Cited
US5712208A
Cited
US5600165A
Cited
US5731220A
Cited
US5796151A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-08 | 2002-09-07 | 2003-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-08 | 2006-09-07 | 2007-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-08 | 2010-09-07 | 2011-03-09 | $7700.00 | Window Closed / Lapsed |