Patent US5889335A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5889335A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device and method of manufacturing the same

Assignee: Renesas Electronics Corp
•
Filing: 1998-02-23
•
Granted: 1999-03-30
•
Expires: 2018-02-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

Inventors

  • 👤 Takashi Kuroi
  • 👤 Maiko Sakai
  • 👤 Katsuyuki Horita
  • 👤 Hirokazu Sayama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 17:42
CPC Classifications
H; H10; H10W; H10W10/00; H10W46/00; H10P; H10P50/00; H10P50/71; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10W46/301; H10W46/501; Y; Y10; Y10S; Y10S438/00; Y10S438/975

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 171 words
A semiconductor device in which semiconductor elements are isolated from each other by a trench-type element isolation structure, comprising: a semiconductor substrate; and an alignment mark area which is formed on said semiconductor substrate, said alignment mark area including a first trench which is formed in an upper portion of said semiconductor substrate and an intra-alignment mark insulation film formed in an under portion which is formed within said first trench, wherein the height of a surface of said intra-alignment mark insulation film is lower than the height of a surface of said semiconductor substrate, and said semiconductor device further comprises: an element formation region which is formed in said semiconductor substrate, said element formation region including an element-isolation insulation film for which isolates a plurality of semiconductor elements from each other, said element-isolation insulation film filling up a second trench which is formed on said upper portion of said semiconductor substrate; and a first dummy layer which is formed covering at least an edge proximity region of said first trench.
Claim 2
Dependent Claim 171 words
A semiconductor device in which semiconductor elements are isolated from each other by a trench-type element isolation structure, comprising: a semiconductor substrate; and an alignment mark area which is formed on said semiconductor substrate, said alignment mark area including a first trench which is formed in an upper portion of said semiconductor substrate and an intra-alignment mark insulation film formed in an under portion which is formed within said first trench, wherein the height of a surface of said intra-alignment mark insulation film is lower than the height of a surface of said semiconductor substrate, and said semiconductor device further comprises: an element formation region which is formed in said semiconductor substrate, said element formation region including an element-isolation insulation film for which isolates a plurality of semiconductor elements from each other, said element-isolation insulation film filling up a second trench which is formed on said upper portion of said semiconductor substrate; and a first dummy layer which is formed covering at least an edge proximity region of said first trench.
Claim 3
Dependent Claim 36 words
The semiconductor device of claim 1, further comprising a gate electrode portion which is formed on said element formation region, wherein said gate electrode portion is formed by the same material as said first dummy layer.
Claim 4
Dependent Claim 63 words
The semiconductor device of claim 2, wherein said first dummy layer is formed covering said first trench including said intra-alignment mark insulation film, and a height difference is formed in said first dummy layer in such a manner that said height difference reflects a preliminary height difference between the surface of said intra-alignment mark insulation film and the surface of said semiconductor substrate.
Claim 5
Dependent Claim 89 words
The semiconductor device of claim 3, further comprising: a diffusion region which is formed adjacent to said gate electrode portion in a surface of said gate electrode portion; an insulation layer which is formed entirely over said semiconductor substrate including said first dummy layer and said gate electrode portion, said insulation layer including a through hole which is formed on said diffusion region in such a manner to penetrate itself; and a diffusion region connecting conduction layer which is electrically connected to said diffusion region through said through hole.
Claim 6
Dependent Claim 32 words
The semiconductor device of claim 4, further comprising a second dummy layer which is formed on a predetermined region of said alignment region other than said first trench of said alignment region.
Claim 7
Dependent Claim 29 words
The semiconductor device of claim 1, wherein the surface of said intra-alignment mark insulation film is lower than the surface of said semiconductor substrate by 30 nm or more.
Claim 8
Dependent Claim 28 words
The semiconductor device of claim 1, wherein the materials of said gate electrode portion and said first dummy layer contain a metal layer or a metal compound layer.

References Cited (Backward Citations)

US4717687A Cited
US4737468A Cited
US4992394A Cited
US5369050A Cited
US5578519A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-03-29 2002-09-28 2003-03-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-03-29 2006-09-28 2007-03-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-03-29 2010-09-28 2011-03-30 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag