Frequency synthesizer with low jitter noise

Claim 3

The apparatus of claim 1, wherein the phase detector includes: a first flip-flop for outputting an up signal by latching a supply voltage and applying the input signal to a clock terminal of the first flop; a second flip-flop for outputting a down signal by latching the supply voltage and applying the frequency-divided signal to a clock terminal of the second flip flop; an AND-gate for ANDing the up and down signals; and series inverters for sequentially inverting an output of the AND-gate and for generating a reset signal and an inverted reset signal for resetting the first and second flip-flops.

Claim 4

The apparatus of claim 2, wherein each of the first and second flip flops includes: first, second, third, fourth, fifth, sixth and seventh PMOS transistors; first, second, third, fourth, fifth and sixth NMOS transistors; and a latch having first and second inputs; wherein sources of the first, second, third, fourth, fifth and seventh PMOS transistors are connected to the supply voltage, wherein drains of the first, second and third PMOS transistors are connected to the first input of the latch and to a gate of the fourth PMOS transistor, wherein drains of the fourth and sixth PMOS transistors are connected to a gate of the third PMOS transistor and to the second input of the latch, wherein a source of the sixth PMOS transistor is connected to a drain of the fifth PMOS transistor, wherein gates of the second and fifth PMOS transistors and gates of the first and second NMOS transistors are connected to a clock, wherein gates of the fifth PMOS transistor and the sixth NMOS transistor are connected to the reset signal, wherein gates of the first PMOS transistor and the third NMOS transistor are connected to the inverted reset signal, wherein sources of the third, fourth, fifth and sixth NMOS transistors are connected to a ground voltage, wherein a drain of the fifth NMOS transistor is connected to a drain of the seventh PMOS transistor, to a source of the second NMOS transistor and to a gate of the fourth NMOS transistor, wherein drains of the sixth and second NMOS transistors are connected to the second input of the latch, and wherein drains of the third and fourth NMOS transistors are connected to a source of the first NMOS transistor and to a gate of the fifth NMOS transistor.

Claim 5

The apparatus of claim 1, wherein the frequency divider includes a divider for dividing an output frequency of the prescaler by a power of two and for outputting the frequency-divided signal to the phase detector as an input signal.

Claim 6

The apparatus of claim 4, wherein the prescaler includes: first, second and third flip flops having first, second and third D outputs, respectively; first and second OR gates; and a NAND gate, wherein a clock is applied to clock terminals of the first and second flip flops, wherein the second D output is applied to a clock terminal of the third flip flop, wherein a mode control signal and the third D outputs are applied to input terminals of the second OR gate, wherein an output of the second OR gate and the first D output are applied to input terminals of the first OR gate, and wherein an output of the first OR gate and the second D output are applied to input terminals of the NAND gate.

Claim 7

The apparatus of claim 5, wherein the first and second flip-flops are each operated as a synchronous counter.

Claim 8

The apparatus of claim 5, wherein the third flip-flop is operated as an asynchronous counter.

Claim 9

The apparatus of claim 5, wherein each of the first, second and third flip flops includes: first, second, third and fourth PMOS transistors; first, second, third and fourth NMOS transistors; first and second inverters; a D input and an inverted D input; and a latch having first and second inputs, wherein sources of the first, second, third and fourth PMOS transistors are connected to a supply voltage, wherein sources of the second and third NMOS transistors are connected to a ground voltage, wherein drains of the first and second PMOS transistors are connected to the first input of the latch, to a gate of the third PMOS transistor and to a drain of the first NMOS transistor, wherein drains of the third and fourth PMOS transistors are connected to the second input of the latch, to a gate of the second PMOS transistor and to a drain of the fourth NMOS transistor, wherein a source of the first NMOS transistor is connected to a drain of the second NMOS transistor, to a gate of the third NMOS transistor and to an output of the first inverter, wherein a source of the fourth NMOS transistor is connected to a drain of the third NMOS transistor, to an output of the second inverter and to a gate of the second NMOS transistor, wherein the clock is connected to gates of the first and fourth PMOS transistors and to gates of the first and fourth NMOS transistors, wherein the D input is connected to an input of the first inverter, and wherein the inverted D input is connected to an input of the second inverter.

Claim 10

The apparatus of claim 1, wherein the voltage controlled oscillator includes: an odd number of delay cells coupled in series for outputting the frequency signal according to the output of the charge pump and the loop filter and according to control signals; and a cell bias circuit for outputting a delay control signal to the delay cells using the first, second and third reference voltages as inputs.

Claim 11

The apparatus of claim 9, wherein the cell bias circuit includes: first and second PMOS transistors; first and second NMOS transistors; and first and second amplifiers for outputting the control signals and each having inverting and non-inverting inputs, wherein a source of the first PMOS transistor is connected to a supply voltage, wherein a gate of the first PMOS transistor is connected to a control voltage, wherein a drain of the first PMOS transistor is connected to the inverting input of the first amplifier and a source of the second PMOS transistor, wherein a gate of the second PMOS transistor is connected to a first control signal, wherein a drain of the second PMOS transistor is connected to the inverting input of the second amplifier and to a drain of the first NMOS transistor, wherein a gate of the first NMOS transistor is connected to the second reference voltage, wherein a source of the first NMOS transistor is connected to a drain of the second NMOS transistor, wherein a gate of the second NMOS transistor is connected to a second control signal, wherein a source of the second NMOS transistor is connected to a ground voltage, wherein the non-inverting input of the first amplifier is connected to the first reference voltage, and wherein the non-inverting input of the second amplifier is connected to the third reference voltage.

Claim 12

The apparatus of claim 9, wherein the delay cell includes: first, second and third PMOS transistors; and first, second and third NMOS transistors, wherein a source of the first PMOS transistor is connected to a supply voltage, wherein a gate of the first PMOS transistor is connected to a control voltage, wherein a drain of the first PMOS transistor is connected to sources of the second and third PMOS transistors, wherein gates of the second and third PMOS transistors are connected to a first control signal, wherein drains of the second and third PMOS transistors are connected to drains of the second and third NMOS transistors, respectively, wherein gates of the second and third NMOS transistors are connected to the output of the charge pump and the loop filter, wherein sources of the second and third NMOS transistors are connected to a drain of the first NMOS transistor, wherein a gate of the first NMOS transistor is connected to a second control signal, and wherein a source of the first NMOS transistor is connected to a ground voltage.

Claim 13

A frequency synthesizer comprising: a phase detector for comparing an input signal with a reference frequency signal and for detecting a phase difference therebetween; a charge pump and a loop filter for differentially amplifying an output of the phase detector for generating a control voltage corresponding to the phase difference; a voltage controlled oscillator for generating a frequency signal corresponding to an output voltage of the charge pump and the loop filter; a frequency divider for dividing the frequency signal generated by the voltage controlled oscillator by a predetermined number and for outputting a frequency-divided signal to the phase detector, wherein the frequency divider includes a prescaler adapted to divide the frequency signal by an odd number; and a reference voltage generator for inputting first, second and third reference voltages to the voltage controlled oscillator for controlling the frequency signal, wherein the voltage controlled oscillator includes: first, second and third voltage controlled delay cells coupled in series; and a bias circuit for controlling each voltage controlled delay cell by using the reference voltages, wherein outputs of the first voltage controlled delay cell are inputs of the second voltage controlled delay cell, wherein outputs of the second voltage controlled delay cell are inputs of the third voltage controlled delay cell, and wherein outputs of the third voltage controlled delay cell are inputs of the first voltage controlled delay cell.

Claim 14

A frequency synthesizer comprising: a phase detector for comparing an input signal with a reference frequency signal and for detecting a phase difference therebetween; a charge pump and a loop filter for differentially amplifying an output of the phase detector for generating a control voltage corresponding to the phase difference; a voltage controlled oscillator for generating a frequency signal corresponding to an output voltage of the charge pump and the loop filter; a frequency divider for dividing the frequency signal generated by the voltage controlled oscillator by a predetermined number and for outputting a frequency-divided signal to the phase detector, wherein the frequency divider includes a prescaler adapted to divide the frequency signal by an odd number; and a reference voltage generator for inputting first, second and third reference voltages to the voltage controlled oscillator for controlling the frequency signal, wherein the voltage controlled oscillator includes: first, second and third voltage controlled delay cells coupled in series; and a bias circuit for controlling each voltage controlled delay cell by using the reference voltages, wherein outputs of the first voltage controlled delay cell are inputs of the second voltage controlled delay cell, wherein outputs of the second voltage controlled delay cell are inputs of the third voltage controlled delay cell, and wherein outputs of the third voltage controlled delay cell are inputs of the first voltage controlled delay cell.

Claim 15

The frequency synthesizer of claim 12, wherein each of the voltage controlled delay cells in the voltage controlled oscillator includes: first, second and third PMOS transistors; and first, second and third NMOS transistors, wherein a source of the first PMOS transistor is connected to a supply voltage, wherein a gate of the first PMOS transistor is connected to sources of the second and third PMOS transistors, wherein gates of the second and third PMOS transistors are connected to a first control signal, wherein drains of the second and third PMOS transistors are connected to drains of the second and third NMOS transistors, wherein gates of the second and third NMOS transistors are connected to an input voltage, wherein sources of the second and third NMOS transistors are connected to a drain of the first NMOS transistor, wherein a gate of the first NMOS transistor is connected to a second control signal, and wherein a source of the first NMOS transistor is connected to a ground voltage.