Patent US5901330A successfully refreshed from Google Patents.
US5901330A
Expired / Lapsed
US
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In-circuit programming architecture with ROM and flash memory
Assignee: Macronix International Co Ltd
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Filing: 1997-03-13
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Granted: 1999-05-04
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Expires: 2017-03-13
Abstract
Abstract An architecture for an integrated circuit with in-circuit programming includes a microcontroller on an integrated circuit and one or more banks of non-volatile memory which store instructions, including an in-circuit programming (ICP) set of instructions. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a device external to the integrated circuit and uses data obtained in the exchange to update software for the microcontroller. Portions of the ICP code which are likely to change between different application environments are stored in reprogrammable flash memory cells. Other portions of the ICP code, which are not likely to change between different application environments, are stored in space-efficient mask ROM memory cells. In this way, the ICP system can be flexibly adapted to different application environments, while conserving on silicon area occupied the ICP system.
Inventors
- 👤 Albert C. Sun
- 👤 Chang-Lun Chen
- 👤 Chee-Horng Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:03
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06F; G06F8/00; G06F8/60; G06F8/65; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/355; G06Q20/3552
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
118 words
An apparatus for in-circuit programming of an integrated circuit, comprising: a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; and a second memory array on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.
Claim 2
Independent Claim
118 words
An apparatus for in-circuit programming of an integrated circuit, comprising: a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; and a second memory array on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.
Claim 3
Dependent Claim
26 words
The apparatus for in-circuit programming of claim 1, wherein the non-volatile memory cells in the first memory array comprise a plurality of floating gate memory cells.
Claim 4
Dependent Claim
20 words
The apparatus for in-circuit programming of claim 1, wherein the second memory array comprises a plurality of non-volatile memory cells.
Claim 5
Dependent Claim
20 words
The apparatus for in-circuit programming of claim 1, wherein the second memory array comprises a plurality of mask ROM cells.
Claim 6
Dependent Claim
21 words
The apparatus for in-circuit programming of claim 1, wherein the second memory array comprises a plurality of floating gate memory cells.
Claim 7
Dependent Claim
34 words
The apparatus for in-circuit programming of claim 1, wherein the sequencing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor.
Claim 8
Dependent Claim
45 words
The apparatus for in-circuit programming of claim 1, wherein the sequencing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.
Claim 9
Dependent Claim
33 words
The apparatus for in-circuit programming of claim 6, wherein the processor controls the erasing, programming and verifying operations for the first memory array through a control register coupled to the first memory array.
Claim 10
Dependent Claim
32 words
The apparatus for in-circuit programming of claim 1, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a timer function included in the processor.
Claim 11
Dependent Claim
33 words
The apparatus for in-circuit programming of claim 1, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor.
Claim 12
Dependent Claim
44 words
The apparatus for in-circuit programming of claim 1, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.
Claim 13
Dependent Claim
32 words
The apparatus for in-circuit programming of claim 1, further including a watch dog timer coupled to the processor which triggers recovery from errors during the processor's execution of the in-circuit programming instructions.
Claim 14
Dependent Claim
24 words
The apparatus for in-circuit programming of claim 1, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.
Claim 15
Dependent Claim
16 words
The apparatus for in-circuit programming of claim 1, wherein the external port comprises a serial port.
Claim 16
Dependent Claim
16 words
The apparatus for in-circuit programming of claim 1, wherein the external port comprises a parallel port.
Claim 17
Dependent Claim
24 words
The apparatus for in-circuit programming of claim 1, wherein the external port is configurable to operate as a parallel port or a serial port.
Claim 18
Dependent Claim
46 words
The apparatus for in-circuit programming of claim 1, including a plurality of ports to external data sources, and wherein the port in the plurality of ports used for the external port is determined by instructions in the set of instructions for controlling the in-circuit programming steps.
Claim 19
Independent Claim
151 words
An apparatus for in-circuit programming of an integrated circuit, comprising: a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising floating gate memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; a second memory array comprising mask ROM cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling, sequencing and timing of the in-circuit programming steps of erasing, programming, and verifying the instructions in the first memory array; and a control register coupled to the first memory array through which the processor controls the erasing, programming, and verifying in the first memory array.
Claim 20
Independent Claim
151 words
An apparatus for in-circuit programming of an integrated circuit, comprising: a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising floating gate memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; a second memory array comprising mask ROM cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling, sequencing and timing of the in-circuit programming steps of erasing, programming, and verifying the instructions in the first memory array; and a control register coupled to the first memory array through which the processor controls the erasing, programming, and verifying in the first memory array.
Claim 21
Dependent Claim
32 words
The apparatus for in-circuit programming of claim 18, further including a watch dog timer coupled to the processor which triggers recovery from errors during the processor's execution of the in-circuit programming instructions.
Claim 22
Dependent Claim
24 words
The apparatus for in-circuit programming of claim 18, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.
Claim 23
Dependent Claim
16 words
The apparatus for in-circuit programming of claim 18, wherein the external port comprises a serial port.
Claim 24
Dependent Claim
16 words
The apparatus for in-circuit programming of claim 18, wherein the external port comprises a parallel port.
Claim 25
Dependent Claim
24 words
The apparatus for in-circuit programming of claim 18, wherein the external port is configurable to operate as a parallel port or a serial port.
Claim 26
Dependent Claim
47 words
The apparatus for in-circuit programming of claim 18, including a plurality of ports to external data sources, and wherein the port in the plurality of ports used for the external port is determined by the instructions in the set of instructions for controlling the in-circuit programming steps.
Claim 27
Dependent Claim
120 words
In an integrated circuit including a processor and an external port, a method for in-circuit programming of the integrated circuit, comprising: providing on the integrated circuit a first memory array comprising non-volatile memory cells, and a second memory array; receiving an in-circuit program command from an initiator external to the integrated circuit; in response to the in-circuit program command, using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions in the first memory array; and using the processor to execute a set of instructions from the first memory array to control the transfer of a set instructions into the integrated circuit from an external source through the external port.
Claim 28
Dependent Claim
120 words
In an integrated circuit including a processor and an external port, a method for in-circuit programming of the integrated circuit, comprising: providing on the integrated circuit a first memory array comprising non-volatile memory cells, and a second memory array; receiving an in-circuit program command from an initiator external to the integrated circuit; in response to the in-circuit program command, using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions in the first memory array; and using the processor to execute a set of instructions from the first memory array to control the transfer of a set instructions into the integrated circuit from an external source through the external port.
Claim 29
Dependent Claim
41 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions in the first memory array is stored in the second memory array.
Claim 30
Dependent Claim
27 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the non-volatile memory cells in the first memory array comprise floating gate memory cells.
Claim 31
Dependent Claim
24 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the second memory array comprises a plurality of mask ROM cells.
Claim 32
Dependent Claim
24 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the second memory array comprises a plurality of non-volatile memory cells.
Claim 33
Dependent Claim
25 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the second memory array comprises a plurality of floating gate memory cells.
Claim 34
Dependent Claim
48 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the step of using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions includes controlling the sequencing of the erasing, programming and verifying operations.
Claim 35
Dependent Claim
37 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the processor controls the erasing, programming and verifying operations for the first memory array through a control register coupled to the first memory array.
Claim 36
Dependent Claim
36 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a timer function included in the processor.
Claim 37
Dependent Claim
48 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the step of using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions includes controlling the timing of the erasing, programming and verifying operations.
Claim 38
Dependent Claim
39 words
The method for in-circuit programming of the integrated circuit of claim 25, including the step of providing a watch dog timer coupled to the processor which triggers recovery from errors during the processor's execution of the in-circuit programming instructions.
Claim 39
Dependent Claim
28 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.
Claim 40
Dependent Claim
20 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the external port comprises a serial port.
Claim 41
Dependent Claim
20 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the external port comprises a parallel port.
Claim 42
Dependent Claim
28 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the external port is configurable to operate as a parallel port or a serial port.
Claim 43
Dependent Claim
63 words
The method for in-circuit programming of the integrated circuit of claim 25, wherein the integrated circuit further includes a plurality of ports to external data sources, and further including the step of determining the port in the plurality of ports used for the external port by using the processor to execute instructions in the set of instructions for controlling the in-circuit programming steps.
Claim 44
Independent Claim
125 words
An apparatus for in-circuit programming of an integrated circuit, comprising: a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising electrically programmable non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; and a second memory array comprising read only memory (ROM) on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.
Claim 45
Independent Claim
125 words
An apparatus for in-circuit programming of an integrated circuit, comprising: a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising electrically programmable non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; and a second memory array comprising read only memory (ROM) on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.
Claim 46
Dependent Claim
26 words
The apparatus for in-circuit programming of claim 41, wherein the nonvolatile memory cells in the first memory array comprise a plurality of floating gate memory cells.
Claim 47
Dependent Claim
20 words
The apparatus for in-circuit programming of claim 41, wherein the second memory array comprises a plurality of mask ROM cells.
Claim 48
Dependent Claim
45 words
The apparatus for in-circuit programming of claim 41, wherein the sequencing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.
Claim 49
Dependent Claim
44 words
The apparatus for in-circuit programming of claim 41, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.
Claim 50
Dependent Claim
24 words
The apparatus for in-circuit programming of claim 41, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.
Claim 51
Dependent Claim
16 words
The apparatus for in-circuit programming of claim 41, wherein the external port comprises a serial port.
Claim 52
Dependent Claim
16 words
The apparatus for in-circuit programming of claim 41, wherein the external port comprises a parallel port.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |