Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the cells to desired values

Claim 2

In an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold voltage level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being addressable to individually read and program their states, a method of operating the array, comprising: utilizing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of alterable states of the individual cells in excess of two, whereby the cells individually store more than one bit of data, applying reset voltages to the cells within at least one block to drive the effective threshold voltages thereof to a reset state, receiving more than one bit of data to be stored in the memory cell array, applying programming voltages to at least one addressed cell within said at least one block in a reset state to drive the effective threshold voltage of said at least one addressed cell toward one of said alterable states that corresponds to the received data, monitoring the state of said at least one addressed cell, comparing the monitored state of said at least one addressed cell with a condition representing the received data, and terminating application of the programming voltages to said at least one addressed cell in response to the monitored state reaching one of the alterable states corresponding to the received data, whereby the state of said at least one addressed cell is programmed to one of said plurality of alterable states.

Claim 3

The operating method of claim 1, wherein applying programming voltages includes applying a programming voltage pulse to said addressed cell for a predetermined time sufficient to move the effective threshold voltage level of said at least one addressed cell from the reset level toward said one of the alterable states that corresponds to the received data, and wherein monitoring the state of said at least one addressed cell includes thereafter reading an electrical parameter of the addressed cell to determine whether the state of said at least one addressed cell has reached the alterable state that corresponds to the received data, and wherein the method additionally comprises repeatedly applying the voltage pulse and reading an electrical parameter until it is determined that the monitored state of said at least one addressed cell has reached that corresponding to the received more than one bit of data.

Claim 4

The operating method of claim 2, wherein the pulse is of a voltage for said predetermined time such that the effective threshold voltage of the addressed cell is changed by less than one-half a difference between two adjacent of said plurality of effective threshold voltage levels.

Claim 5

The operating method of claim 2 wherein repeating of the voltage pulse applying and reading steps is terminated after a preset maximum number of such repeats have occurred without programming the effective threshold voltage levels of the addressed cell to said desired state.

Claim 6

The operating method of claim 1, wherein applying reset voltages to the cells within said at least one block to drive the effective threshold voltages thereof to a reset state includes: applying a reset voltage pulse to the cells within said at least one block for a predetermined time sufficient to move the effective threshold voltage levels of the cells within said at least one block toward said reset state, thereafter reading an electrical parameter of the cells within said at least one block to determine whether the individual cells within said at least one block have reached said reset state, and repeating the foregoing voltage pulse applying and reading steps within said at least one block until it is detected that the effective threshold voltage of the cells within said at least one block have been driven to said reset state.

Claim 7

The operating method of claim 5 wherein the voltage of the reset pulse increases as the voltage applying and reading steps are repeated.

Claim 8

The operating method of claim 5 wherein the repeating of the voltage pulse applying and reading steps during resetting the effective threshold voltage levels of cells within said at least one block is terminated after a preset maximum number of repeats of the voltage applying and reading steps have occurred without resetting the effective threshold voltage level of at least a certain number of the individual cells within said at least one block to said reset level.

Claim 9

The operating method of claim 1 wherein said reset state is designated as one of said alterable states.

Claim 10

The operating method of any one of claims 1-8, wherein monitoring the state of said at least one addressed cell includes electrically interrogating the addressed cell and comparing a resulting level of an electrical parameter of the addressed cell with a number of reference levels of two or more.

Claim 11

The operating method of claim 9, wherein the resulting electrical parameter level is compared simultaneously with said number of reference levels of two or more.

Claim 12

The operating method of any one of claims 1-8, wherein at least two of said plurality of effective threshold levels result from a net positive charge on the floating gate of the individual cells.

Claim 13

The operating method of any one of claims 1-8, wherein the field effect transistors of the memory cells are characterized by a natural threshold level in excess of three volts in the absence of any charge on the floating gate.

Claim 14

The operating method of any one of claims 1-8, which additionally comprises, in response to said at least one addressed cell becoming defective, of substituting therefore a redundant good cell within the array.

Claim 15

The operating method of any one of claims 1-8, which additionally comprises, in response to said at least one block of cells becoming defective, of substituting therefore at least one redundant block of cells within the array.

Claim 16

The operating method of any one of claims 1-8 which additionally comprises accumulating a count of a total number of times that said at least one block of cells has been reset.

Claim 17

An electrically erasable programmable read only memory system, comprising: an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being individually addressable to program them into one of more than two distinct programmable threshold levels corresponding to more than one bit of input data per cell, a reset circuit that simultaneously applies reset voltages to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state, a programming circuit that applies programming voltages to at least one addressed cell within a reset block to drive the effective threshold voltage of said at least one addressed cell toward one of the more than two programmable threshold levels corresponding to the input data being stored therein, a reading circuit that monitors the threshold of said at least one addressed cell, and a comparator having inputs of the monitored threshold of said at least one addressed cell, the input data being stored in said at least one addressed cell and two or more reference levels discriminating between more than two programmable threshold levels, and having an output that terminates application of programming voltages to said at least one addressed cell when the monitored threshold reaches the programmable threshold level corresponding to the input data, whereby more than one bit of input data is programmed into said at least one addressed cell.

Claim 18

An electrically erasable programmable read only memory system, comprising: an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being individually addressable to program them into one of more than two distinct programmable threshold levels corresponding to more than one bit of input data per cell, a reset circuit that simultaneously applies reset voltages to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state, a programming circuit that applies programming voltages to at least one addressed cell within a reset block to drive the effective threshold voltage of said at least one addressed cell toward one of the more than two programmable threshold levels corresponding to the input data being stored therein, a reading circuit that monitors the threshold of said at least one addressed cell, and a comparator having inputs of the monitored threshold of said at least one addressed cell, the input data being stored in said at least one addressed cell and two or more reference levels discriminating between more than two programmable threshold levels, and having an output that terminates application of programming voltages to said at least one addressed cell when the monitored threshold reaches the programmable threshold level corresponding to the input data, whereby more than one bit of input data is programmed into said at least one addressed cell.

Claim 19

The memory system of claim 16, wherein the programming circuit applies a sequence of programming voltage pulses to said at least one addressed cell and the reading circuit monitors the threshold of said at least one addressed cell in between said pulses.

Claim 20

The memory system of claim 16, wherein the reset circuit applies a sequence of reset voltage pulses to the cells within at least one block, the reading circuit monitors the threshold of the cells within said at least one block in between said pulses, and said comparator terminates application of reset voltages when the monitored threshold of the cells within said block reaches said reset state.

Claim 21

The memory system of claim 16, wherein at least two of said more than two distinct threshold levels result from a net positive charge on the floating gate of the individual cells.

Claim 22

The memory system of any one of claims 16-19, which additionally comprises another circuit that responds to said at least one addressed cell becoming defective to substitute therefore a redundant good cell within the array.

Claim 23

The memory system of any one of claims 16-19, which additionally comprises another circuit that responds to a block of cells becoming defective to substitute therefore a redundant good block of cells within the array.

Claim 24

The memory system of any one of claims 16-19, which additionally comprises another circuit that accumulates a count of a total number of times that said at least one block of cells has been reset.

Claim 25

An electrically erasable programmable read only memory system, comprising: an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being individually addressable to program them into one of more than two distinct programmable threshold levels corresponding to more than one bit of input data per cell, a reset circuit that simultaneously applies reset voltages to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state, a programming circuit that applies repetitive programming voltage pulses to at least one addressed cell within a reset block to drive the effective threshold voltage of said at least one addressed cell toward one of the more than two programmable threshold levels corresponding to a designated more than one bit of input data being stored therein, and a reading circuit that monitors the threshold of said at least one addressed cell in between said programming pulses in order to cause the programming pulses to terminate when the monitored threshold reaches the programmable threshold level corresponding to said designated more than one bit of input data.

Claim 26

An electrically erasable programmable read only memory system, comprising: an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being individually addressable to program them into one of more than two distinct programmable threshold levels corresponding to more than one bit of input data per cell, a reset circuit that simultaneously applies reset voltages to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state, a programming circuit that applies repetitive programming voltage pulses to at least one addressed cell within a reset block to drive the effective threshold voltage of said at least one addressed cell toward one of the more than two programmable threshold levels corresponding to a designated more than one bit of input data being stored therein, and a reading circuit that monitors the threshold of said at least one addressed cell in between said programming pulses in order to cause the programming pulses to terminate when the monitored threshold reaches the programmable threshold level corresponding to said designated more than one bit of input data.

Claim 27

The memory system of claim 23, wherein said reset circuit simultaneously applies repetitive resetting voltage pulses to the cells within at least one of said blocks, and said reading circuit monitors the thresholds of the cells within said at least one of said blocks in between said resetting pulses in order to cause the resetting pulses to terminate when the monitored threshold of the cells reaches the reset state.

Claim 28

The memory system of claim 23, wherein said reading circuit includes a comparator circuit having inputs connectable to said at least one addressed cell and to said designated more than one bit of input data, and an output connected to the programming means to cause said termination of the programming pulses.

Claim 29

The memory system of any one of claims 23-25, which additionally comprises another circuit that responds to said at least one addressed cell becoming defective to substitute therefore a redundant good cell within the array.

Claim 30

The memory system of any one of claims 23-25, which additionally comprises another circuit that responds to a block of cells becoming defective to substitute therefore a redundant good block of cells within the array.

Claim 31

The memory system of any one of claims 23-25, which additionally comprises another circuit that accumulates a count of a total number of times that said at least one block of cells has been reset.

Claim 32

An electrically erasable programmable read only memory (EEPROM) system, comprising: a semiconductor substrate including an array of a plurality of storage cells arranged in rows and columns across said substrate, the individual cells having a transistor including: a source region and a drain region formed in said substrate with a channel therebetween, a floating gate positioned over at least a portion of the channel in a manner that a level of charge on the floating gate establishes a threshold level of conductance through the channel between the source and drain regions, and a control gate extending across the floating gate in a manner that a level of electrical potential on the control gate affects the level of conductance of the channel between the source and drain regions, programming means connectable to at least one addressed cell within the array of cells for applying voltages to the transistor of the addressed cell to alter the charge on its floating gate, thereby to alter the threshold level of the transistor of the addressed cell, reading means connectable to at least one addressed cell within the array of cells for detecting a level of conductance between the source and drain regions of the addressed cell in response to a predetermined voltage being applied across the source and drain regions of the addressed cell transistor and a predetermined potential level being applied to the control gate of the addressed cell transistor, erasing means connectable to electrodes of cells within one of a plurality of distinct blocks of cells of the array for simultaneously removing electrical charge from the floating gates of the cells within said one block that is sufficient to drive the threshold levels of the transistors of said one block of cells to an erased level, said reading means includes means for discriminating between a plurality of more than two predetermined threshold levels of the addressed cell transistor, each cell thereby having a corresponding plurality of storage states more than two, and said programming means includes means for applying programming voltage to the addressed cell transistor to alter the charge on its floating gate, means responsive to the threshold level detected by said reading means for comparing the read threshold level with that corresponding to the data being programmed into the transistor of the addressed cell, and means responsive to a comparison of the read threshold level with a desired one of the more than two threshold levels for terminating application of the programming voltage to the addressed cell.

Claim 33

An electrically erasable programmable read only memory (EEPROM) system, comprising: a semiconductor substrate including an array of a plurality of storage cells arranged in rows and columns across said substrate, the individual cells having a transistor including: a source region and a drain region formed in said substrate with a channel therebetween, a floating gate positioned over at least a portion of the channel in a manner that a level of charge on the floating gate establishes a threshold level of conductance through the channel between the source and drain regions, and a control gate extending across the floating gate in a manner that a level of electrical potential on the control gate affects the level of conductance of the channel between the source and drain regions, programming means connectable to at least one addressed cell within the array of cells for applying voltages to the transistor of the addressed cell to alter the charge on its floating gate, thereby to alter the threshold level of the transistor of the addressed cell, reading means connectable to at least one addressed cell within the array of cells for detecting a level of conductance between the source and drain regions of the addressed cell in response to a predetermined voltage being applied across the source and drain regions of the addressed cell transistor and a predetermined potential level being applied to the control gate of the addressed cell transistor, erasing means connectable to electrodes of cells within one of a plurality of distinct blocks of cells of the array for simultaneously removing electrical charge from the floating gates of the cells within said one block that is sufficient to drive the threshold levels of the transistors of said one block of cells to an erased level, said reading means includes means for discriminating between a plurality of more than two predetermined threshold levels of the addressed cell transistor, each cell thereby having a corresponding plurality of storage states more than two, and said programming means includes means for applying programming voltage to the addressed cell transistor to alter the charge on its floating gate, means responsive to the threshold level detected by said reading means for comparing the read threshold level with that corresponding to the data being programmed into the transistor of the addressed cell, and means responsive to a comparison of the read threshold level with a desired one of the more than two threshold levels for terminating application of the programming voltage to the addressed cell.

Claim 34

The EEPROM system of claim 29, wherein the individual cells include an erase electrode positioned adjacent said floating gate.

Claim 35

The EEPROM system of claim 29, wherein said programming voltage applying means includes means for applying a sequence of programming voltage pulses to the addressed cell, and wherein said comparing means operates in between the programming voltage pulses.

Claim 36

The EEPROM system of claim 29 wherein said erasing means includes means for repeating a cycle of applying an erase voltage in a short erase pulse to the cells within the distinct block being erased and then causing said reading means to determine the threshold level of at least some of the cells within that block, the voltage level of an initial erase pulse being insufficient to fully erase the cells of the distinct block being erased and increasing an incremental amount from pulse to pulse.

Claim 37

The EEPROM system of claim 32 wherein said erasing means includes means for incrementing the voltage level of each respective erase voltage pulse after the initial pulse by an amount of the voltage of the initial pulse plus a fixed voltage increment times the number of the respective pulse in a sequence after the first pulse.

Claim 38

The EEPROM system of claim 29 wherein the pulse applying means of the programming means includes means for limiting a magnitude of each of said sequence of voltage pulses to a value that is less than that which shifts the threshold level of the addressed cell transistor one-half a difference between adjacent of said more than two predetermined threshold levels.